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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator february 2005 rev. 1.0.1 general description the xrt83l34 is a fully integrated quad (four channel) long-haul and short-haul line interface unit for t1 (1.544mbps) 100 ? , e1 (2.048mbps) 75 ? or 120 ?, or j1 110 ? applications. in long-haul applications the xrt83l34 accepts signals that have been attenuated from 0 to 36db at 772khz in t1 mode (equivalent of 0 to 6000 feet of cable loss) or 0 to 43db at 1024khz in e1 mode. in t1 applications, the xrt83l34 can generate five transmit pulse shapes to meet the short-haul digital cross-connect (dsx-1) template requirements as well as for channel service units (csu) line build out (lbo) filters of 0db, -7.5db -15db and -22.5db as required by fcc rules. it also provides programmable transmit pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions. the xrt83l34 provides both a parallel host microprocessor interface as well as a hardware mode for programming and control. both the b8zs and hdb3 encoding and decoding functions are selectable as well as ami. an on-chip crystal-less jitter attenuator with a 32 or 64 bit fifo can be placed either in the receive or the transmit path with loop bandwidths of less than 3hz. the xrt83l34 provides a variety of loop-back and diagnostic features as well as transmit driver short circuit detection and receive loss of signal monitoring. it supports internal impedance matching for 75 ?, 100 ?, 110 ? and 120 ? for both transmitter and receiver. in the absence of the power supply, the transmit outputs and receive inputs are tri-stated allowing for redundancy applications the chip includes an integrated programmable clock multiplier that can synthesize t1 or e1 master clocks from a variety of external clock sources. applications ? t1 digital cross-connects (dsx-1) ? isdn primary rate interface ? csu/dsu e1/t1/j1 interface ? t1/e1/j1 lan/wan routers ? public switching syst ems and pbx interfaces ? t1/e1/j1 multiplexer and channel banks features (see page 2) f igure 1. b lock d iagram of the xrt83l34 t1/e1/j1 liu (h ost m ode ) one of four channels, channel_n - (n= 0:3) hw /host wr_r/w rd_ds ale_as cs rdy_dtack int ict tpos_n/tdata_n tneg_n/codes_n tclk_n rclk_n rneg_n/lcv_n rpos_n/rdata_n rlos_n rtip_n rring_n master clock synthesizer qrss pattern generator dmo_n ttip_n tring_n txon_n hdb3/ b8zs encoder tx/rx jitter attenuator timing control tx filter & pulse shaper line driver drive monitor local analog loopback remote loopback digital loopback hdb3/ b8zs decoder tx/rx jitter attenuator timing & data recovery peak detector & slicer qrss detector network loop detector rx equalizer equalizer control ais detector los detector lbo[3:0] loopback enable ja select nlcd enable qrss enable pts1 pts2 d[7:0] pclk a[7:0] reset microprocessor controller test dfm taos enable mclke1 mclkt1 mclkout
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 2 features ? fully integrated four channel long-haul or short- haul transceivers for e1,t1 or j1 applications ? adaptive receive equalizer for up to 36db cable attenuation ? programable transmit pulse shaper for e1,t1 or j1 short-haul interfaces ? five fixed transmit pulse settings for t1 short-haul applications plus a fully programmable waveform generator for transmit output pulse shaping t hat can be used for both t1 and e1 modes. ? transmit line build-outs (lbo) for t1 long-haul app lication from 0db to -22.5db in three 7.5db steps ? selectable receiver sensitivity from 0 to 36db cable loss for t1 @772khz and 0 to 43db for e1 @1024khz ? receive monitor mode handles 0 to 29db resistive at tenuation along with 0 to 6db of cable attenuation for e1 and 0 to 3db of cable attenuation for t1 modes ? supports 75 ? and 120 ? (e1), 100 ? (t1) and 110 ? (j1) applications ? internal and/or external impedance matching for 75 ? , 100 ?, 110 ? and 120 ? ? tri-state transmit ou tput and receive input capab ility for redundanc y applications ? provides high impedance for tx and rx during power off ? transmit return loss meets or exceeds etsi 300-166 standard ? on-chip digital clock recovery circ uit for high input jitter tolerance ? crystal-less digital jitter attenuator with 32-bit or 64-bit fifo selectable either in transmit or receive path ? on-chip frequency multiplier generates t1 or e1 master clocks from variety of external clock sources ? high receiver interference immunity ? on-chip transmit short-circuit protection and limiting, and driver fa il monitor output (dmo) ? receive loss of signal (rlos) output ? on-chip hdb3/b8zs/ami encoder/decoder functions ? qrss pattern generator and detection for testing and monitoring f igure 2. b lock d iagram of the xrt83l34 t1/e1/j1 liu (h ardware m ode ) one of four channels, channel_n - (n=0 : 3) hw/host gauge jasel1 jasel0 rxtsel txtsel tersel1 tersel0 rxres1 rxres0 ict mclke1 mclkt1 clksel[2:0] tpos_n/tdata_n tneg_n/codes_n tclk_n rclk_n rneg_n/lcv_n rpos_n/rdata_n rlos_n rtip_n rring_n master clock synthesizer qrss pattern generator dmo_n ttip_n tring_n txon_n hdb3/ b8zs encoder tx/rx jitter attenuator timing control tx filter & pulse shaper line driver local analog loopback remote loopback digital loopback hdb3/ b8zs decoder tx/rx jitter attenuator timing & data recovery peak detector & slicer qrss detector network loop detector rx equalizer equalizer control ais detector los detector lbo[3:0] loopback enable ja select nlcd enable qrss enable harware control test reset tratio sr/dr eqc[4:0] tclke rclke rxmute ataos drive monitor dfm mclkout taos_n loop1_n loop0_n
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 3 ? error and bipolar violation insertion and detection ? receiver line attenuation indication output in 1db steps ? network loop-code detection for automatic loop-back activation/deactivation ? transmit all ones (taos) and in-band network loop up and down code generators ? supports local analog, remote, digital and dual loop-back modes ? meets or exceeds t1 and e1 short-haul and long-haul network access specificati ons in itu g.703, g.775, g.736 and g.823; tr-tsy-000499; ansi t1.403 and t1.408; etsi 300-166 and at&t pub 62411 ? supports both hardware and host (parallel microprocessor) interface for programming ? programmable interrupt ? low power dissipation ? logic inputs accept either 3.3v or 5v levels ? single 3.3v supply operation ? 128 pin tqfp package ? -40c to +85c temperature range ordering information p art n umber p ackage o perating t emperature r ange xrt83l34iv 128 lead tqfp (14 x 20 x 1.4mm) -40 c to +85 c
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 4 f igure 3. p in o ut of the xrt83l34 xrt83l34 tclk_2 tpos_2/tdata_2 tneg_2/codes_2 upts1/rclke upts2/tclke rxres0 rxres1 rxtsel txtsel tersel1 tersel0 gnd dvdd dvdd dgnd dgnd int/tratio ict reset txon_0 txon_1 txon_2 txon_3 tneg_1/codes_1 tpos_1/tdata_1 tclk_1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 dmo_0 a[0]/eqc0 a[1]/eqc1 a[2]/eqc2 a[3]/eqc3 a[4]/eqc4 a[5]/jasel0 a[6]/jasel1 dgnd dgnd dgnd dvdd dvdd dvdd upclk/ataos d[0]/loop0_3 d[1]/loop1_3 d[2]/loop0_2 d[3]/loop1_2 d[4]/loop0_1 d[5]/loop1_1 d[6]/loop0_0 d[7]/loop1_0 agnd avdd clksel2 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 tclk_3 tpos_3/tdata_3 tneg_3/codes_3 rlos_3 rclk_3 rneg_3/lcv_3 rpos_3/rdata_3 rvdd_3 rtip_3 rring_3 rgnd_3 tgnd_3 ttip_3 tvdd_3 tring_3 gauge tring_2 tvdd_2 ttip_2 tgnd_2 rgnd_2 rring_2 rtip_2 rvdd_2 rpos_2/rdata_2 rneg_2/lcv_2 rclk_2 rlos_2 dgnd rdy_dtack/rxmute cs/taos_3 ale_as/taos_2 rd_ds/taos_1 wr_r/w/taos_0 hw_host dmo_3 dmo_2 dmo_1 tclk_0 tpos_0/tdata_0 tneg_0/codes_0 rlos_0 rclk_0 rneg_0/lcv_0 rpos_0/rdata_0 rvdd_0 rtip_0 rring_0 rgnd_0 tgnd_0 ttip_0 tvdd_0 tring_0 sr/dr tring_1 tvdd_1 ttip_1 tgnd_1 rgnd_1 rring_1 rtip_1 rvdd_1 rpos_1/rdata_1 rneg_1/lcv_1 rclk_1 rlos_1 dvdd vddpll_1 vddpll_2 mclke1 mclkt1 gndpll_1 gndpll_2 mclkout clksel0 clksel1
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 i table of contents general description........... ................ ................ ................. .............. .............. ............1 a pplications ............................................................................................................................... ................. 1 figure 1. block diagram of th e xrt83l34 t1/e1/j1 liu (host mode) ........................................... 1 figure 2. block diagram of the xrt83l34 t1/e1/j1 liu (hardware mode)................................... 2 f eatures ............................................................................................................................... ...................... 2 ordering information ........................................................................................................... ............ 3 figure 3. pin out of the xrt83l34............................................................................................. ....... 4 table of contents ......... ................ ................. ................ ................. .............. ............ i pin description by functi on............... ................. .............. .............. .............. ............5 r eceive s ections ............................................................................................................................... ......... 5 t ransmitter s ections ............................................................................................................................... .9 m icroprocessor i nterface ..................................................................................................................... 13 j itter a ttenuator ............................................................................................................................... ..... 19 c lock s ynthesizer ............................................................................................................................... .... 20 a larm f unction //r edundancy s upport .................................................................................................. 21 p ower and ground ............................................................................................................................... .... 25 functional description ..... ................ ................ ................. .............. .............. .......... 26 m aster c lock g enerator ....................................................................................................................... 26 figure 4. two input clock source.............................................................................................. ..... 26 figure 5. one input clock source......... ................ ................. ................ ............. ............ ........... ..... 26 t able 1: m aster c lock g enerator ................................................................................................ 27 receiver................. ................ ................. .............. .............. .............. .............. ............. .... 27 r eceiver i nput ............................................................................................................................... ........... 27 r eceive m onitor m ode ............................................................................................................................. 28 r eceiver l oss of s ignal (rlos)............................................................................................................. 28 figure 6. simplified diagram of -15db t1/e1 short haul mode and rlos condition ............... 28 figure 7. simplified diagram of -29db t1/e1 gain mode and rl os condition.......................... 29 figure 8. simplified diagra m of -36db t1/e1 long haul mode and rlos condi tion ....... ......... 29 figure 9. simplified diagram of extended rlos mode (e1 only) . .............................................. 30 r eceive hdb3/b8zs d ecoder ................................................................................................................. 30 r ecovered c lock (rclk) s ampling e dge .............................................................................................. 30 figure 10. receive clock and ou tput data timing ....................................................................... 30 j itter a ttenuator ............................................................................................................................... ..... 30 g apped c lock (ja m ust be e nabled in the t ransmit p ath ) .................................................................. 31 t able 2: m aximum g ap w idth for m ultiplexer /m apper a pplications ......................................... 31 a rbitrary p ulse g enerator for t1 and e 1 ........................................................................................... 32 figure 11. arbitrary pulse segment assignment .......................................................................... 32 transmitter .............. ................ ................ .............. .............. ............... .............. ............ 3 2 d igital d ata f ormat ............................................................................................................................... .. 32 t ransmit c lock (tclk) s ampling e dge .................................................................................................. 32 figure 12. transmit cl ock and input data timing ......................................................................... 33 t ransmit hdb3/b8zs e ncoder ................................................................................................................ 33 t able 3: e xamples of hdb3 e ncoding ........................................................................................... 33 t able 4: e xamples of b8zs e ncoding ............................................................................................ 33 d river f ailure m onitor (dmo) ............................................................................................................... 33 t ransmit p ulse s haper & l ine b uild o ut (lbo) circuit ........................................................................ 34 t able 5: r eceive e qualizer c ontrol and t ransmit l ine b uild -o ut s ettings ............................ 34 transmit and receive terminatio ns ............. ................. .............. .............. .......... 36 receiver (c hannels 0 - 3) ..................................................................................................................... 36 internal receive termination mode ....................... ....................................................................... .............. 36 t able 6: r eceive t ermination c ontrol .......................................................................................... 36 figure 13. simplified diagram for the internal receive and transmit termination mode......... 36
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator ii t able 7: r eceive t erminations ........................................................................................................ 37 figure 14. simplified diagram fo r t1 in the external termination mode (rxtsel= 0) .............. 37 figure 15. simplified diagram fo r e1 in external termination mode (rxtsel= 0) .................... 38 transmitter (c hannels 0 - 3) .............................................................................................................. 38 transmit termination mode ...................................................................................................... .................. 38 t able 8: t ransmit t ermination c ontrol ........................................................................................ 38 t able 9: t ermination s elect c ontrol ............................................................................................ 38 external transmit termination mode ............................................................................................. ............. 38 t able 10: t ransmit t ermination c ontrol ...................................................................................... 39 t able 11: t ransmit t erminations .................................................................................................... 39 redundancy applications ........................................................................................................ ....... 39 typical redundancy schemes ..................................................................................................... .. 40 figure 16. simplified block diagram of the tr ansmit section for 1:1 & 1+1 redundancy ........41 figure 17. simplified block diagram - receive section for 1:1 and 1+1 redundancy ............... 41 figure 18. simplified block di agram - transmit section for n+ 1 redundancy .......................... 42 figure 19. simplified block diagram - receive section for n+1 redundancy ............................ 43 p attern t ransmit and d etect f unction ................................................................................................. 44 t able 12: p attern transmission control ....................................................................................... 44 t ransmit a ll o nes (taos) ....................................................................................................................... 4 4 n etwork l oop c ode d etection and t ransmission ................................................................................. 44 t able 13: l oop -c ode d etection c ontrol ...................................................................................... 44 t ransmit and d etect q uasi -r andom s ignal s ource (tdqrss) ........................................................... 45 l oop -b ack m odes ............................................................................................................................... ....... 46 t able 14: l oop - back control in h ardware mode ......................................................................... 46 t able 15: l oop - back control in h ost mode ................................................................................... 46 l ocal a nalog l oop -b ack (aloop).......................................................................................................... 46 figure 20. local analog loop-back signal flow... ................ ................ ................ ................ .......... 46 r emote l oop -b ack (rloop) .................................................................................................................... 47 figure 21. remote loop-back mode with jitter attenuator selected in receive path .................. 47 figure 22. remote loop-back mode with jitter attenuator selected in transmit path ............... 47 d igital l oop -b ack (dloop) ..................................................................................................................... 48 figure 23. digital loop- back mode with jitter attenuator sel ected in transmit path ................. 48 d ual l oop -b ack ............................................................................................................................... ......... 48 figure 24. signal flow in dual loop-back mode.............................................................................. 48 the microprocessor interface..... ............... ................. .............. .............. ........... 49 the pins of the microprocessor interface ............................................................................................ 49 t able 16: m icroprocessor interface signal description ............................................................ 49 operating the microprocessor interface in the intel - asynchronous mode ...................................... 52 t able 17: t he r oles of the v arious m icroprocessor i nterface p ins , when configured to op - erate in the i ntel -a synchronous m ode .............................................................................. 52 c onfiguring the microprocessor interface to operate in the intel - asynchronous m ode .............. 53 the intel - asynchronous read cycle ....................................................................................................... 53 figure 25. illlustration of an intel-asynchronous mode read op eration .............. ............ .......... 54 t he intel - asynchronous write cycle ...................................................................................................... 54 figure 26. illustration of an intel-asynchronous mode write op eration ..................................... 55 o perating the m icroprocessor in terface in the m otorola -a synchronous m ode .......................... 55 ............................................................................................................................... ..................................... 56 t able _, t he r oles of various microprocessor interface pins , when configured to operate in the motorola - asynchronous mode ................................................................................................................ 56 configuring the microprocessor interface to operate in the motorola - asynchronous mode ....... 57 the motorola - asynchronous read - cycle :..............................................................................................57 figure 27. illlustration of a motorola-asynchronous m ode read operation.. ................ ............. 58 t he m otorola - asynchronous write cycle ............................................................................................. 58 figure 28. illustration of a mo torola-asynchronous write operat ion.......................................... 59 m icroprocessor r egister t ables .......................................................................................................... 60
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 iii t able 18: m icroprocessor r egister a ddress .............................................................................. 60 t able 19: m icroprocessor r egister b it d escription .................................................................. 60 m icroprocessor r egister d escriptions ............................................................................................... 63 t able 20: m icroprocessor r egister #0, b it d escription ............................................................ 63 t able 21: m icroprocessor r egister #1, b it d escription ............................................................ 64 t able 22: m icroprocessor r egister #2, b it d escription ............................................................ 66 t able 23: m icroprocessor r egister #3, b it d escription ............................................................ 68 t able 24: m icroprocessor r egister #4, b it d escription ............................................................ 70 t able 25: m icroprocessor r egister #5, b it d escription ............................................................ 71 t able 26: m icroprocessor r egister #6, b it d escription ............................................................ 73 t able 27: m icroprocessor r egister #7, b it d escription ............................................................ 74 t able 28: m icroprocessor r egister #8, b it d escription ............................................................ 75 t able 29: m icroprocessor r egister #9, b it d escription ............................................................ 75 t able 30: m icroprocessor r egister #10, b it d escription .......................................................... 76 t able 31: m icroprocessor r egister #11, b it d escription .......................................................... 76 t able 32: m icroprocessor r egister #12, b it d escription .......................................................... 77 t able 33: m icroprocessor r egister #13, b it d escription .......................................................... 77 t able 34: m icroprocessor r egister #14, b it d escription .......................................................... 78 t able 35: m icroprocessor r egister #15, b it d escription .......................................................... 78 t able 36: m icroprocessor r egister #64, b it d escription .......................................................... 79 clock select register....... ................ ................ ................. .............. .............. .......... 80 figure 29. register 0x81h sub registers .......... ............................................................................. 80 t able 37: m icroprocessor r egister #65, b it d escription .......................................................... 81 t able 38: m icroprocessor r egister #66, b it d escription .......................................................... 82 electrical characteristics ................. .............. .............. .............. .............. ..........84 t able 39: a bsolute m aximum r atings ............................................................................................ 84 t able 40: dc d igital i nput and o utput e lectrical c haracteristics ......................................... 84 t able 41: xrt83l34 p ower c onsumption ..................................................................................... 84 t able 42: e1 r eceiver e lectrical c haracteristics ..................................................................... 85 t able 43: t1 r eceiver e lectrical c haracteristics ..................................................................... 86 t able 44: e1 t ransmit r eturn l oss r equirement ........................................................................ 86 t able 45: e1 t ransmitter e lectrical c haracteristics ............................................................... 87 t able 46: t1 t ransmitter e lectrical c haracteristics ............................................................... 87 figure 30. itu g.703 pulse template........................................................................................... ... 88 t able 47: t ransmit p ulse m ask s pecification .............................................................................. 88 figure 31. dsx-1 pulse template (normalized amplitude) ........................................................... 89 t able 48: dsx1 i nterface i solated pulse mask and corner points ........................................... 89 t able 49: ac e lectrical c haracteristics .................................................................................... 90 figure 32. transmit cl ock and input data timing ......................................................................... 90 figure 33. receive clock and ou tput data timing ....................................................................... 91 m icroprocessor i nterface i/o t iming .................................................................................................... 91 intel interface timing - asynchronous .......................................................................................... .............. 91 figure 34. intel asyn chronous programmed i/o in terface timing .............. ............. ............. ...... 91 t able 50: a synchronous m ode 1 - i ntel 8051 and 80188 i nterface t iming ................................ 92 motorola asychronous interface timi ng ............. .............. .............. .............. .............. ............ ......... ........... 93 figure 35. motorola 68k asynchronous progra mmed i/o interface timing ............ ............. ...... 93 t able 51: a synchronous - m otorola 68k - i nterface t iming s pecification .............................. 93 figure 36. microp rocessor interface timing - reset pulse width ............................................... 93 ordering information ........ ................ ................ ................. .............. .............. .......... 94 p ackage d imensions - 14 x 20 mm , 128 pin package ................................................................................. 94 r evisions ............................................................................................................................... .................... 95 n otes :.............................................................................................................................. ............ 96
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 5 pin description by function receive sections s ignal n ame p in # t ype d escription rlos_0 rlos_1 rlos_2 rlos_3 4 28 75 99 o receiver los (loss of signal) defect indicator output for channel _n this output pin indicates whether or not the receive section associated with channel n (within the liu device) is de claring the los defect condition, as depicted below. logic low - indicates that this particular channel is currently not declaring the los defect condition. logic high - indicates that this partic ular channel is currently declaring the los defect condition. see ?receiver loss of signal (rlos)? on page 28. rclk_0 rclk_1 rclk_2 rclk_3 5 27 76 98 o receiver clock output for channel _n the receive section (of a given channel within the xrt83l34 device) will update the rpos_n and rneg_n/lcv_n ou tput pins upon either the rising or falling edge of this output clock signal (depending upon user configura - tion). rneg_0/ lcv_0 rneg_1/ lcv_1 rneg_2/ lcv_2 rneg_3/ lcv_3 6 26 77 97 o receiver negative-polarity data output/line code violation indicator output - channel n: the exact function of this output pin depends upon whether the xrt83l34 device has been configured to operate in the single-rail or dual-rail mode, as described below. dual-rail mode operation - receive negative-polarity data output - rneg_n: the receive section of channel n will ou tput the negative-po larity portion of the recovered incoming ds 1/e1 data (from the remo te terminal equipment) via this output pin. each channel (within the xrt83l34 device) will update this incoming ds1/e1 data upon the "user-selected" edge of the rclk_n output signal. the "positive-polarity portion" of t he recovered incoming ds1/e1 data will be output via the rpos_n output pin. single-rail mode operation - line code violation indicator output - lcv_n: the receive section of channel n will pu lse this output pin "high" (for one rclk_n period) each time it detects a line code violation within the incom - ing ds1/e1 line signal. each channel (within the xrt83l34 device) will update this output pin upon the "user-s elected" edge of the rclk_n output signal.
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 6 rpos_0/ rdata_0 rpos_1/ rdata_1 rpos_2/ rdata_2 rpos_3/ rdata_3 7 25 78 96 o receiver positive-polarity data output/receive data output - channel n: the exact function of this output pin depends upon whether the xrt83l34 device has been configured to operate in the single-rail or dual-rail mode as described below. dual-rail mode operation - receive po sitive-polarity data output pin - rpos_n: the receive section of channel n will ou tput the positive-polarity portion of the recovered incoming ds1/e1 data (from the remote terminal equipment) via this output pin. each channel (w ithin the xrt83l34 device) will update the data (that is output via this output pin) upon the "user-selected" edge of the rclk_n output clock signal. the "negative-portion" of this reco vered incoming ds1/e1 data (from the remote terminal equipment) will be output via the corresponding rneg_n output pin. single-rail mode operation - receive data output pin - rdata_n if channel n has been configured to operate in the single-rail mode, then the entire incoming ds1/e1 data (that has been recovered by the receive section of channel n) will be output via this output pin upon the "user- selected" edge of the rclk_n output clock signal. rtip_0 rtip_1 rtip_2 rtip_3 9 23 80 94 i receiver differential tip po sitive input fo r channel _n: this input pin, along with the corresp onding rring_n input pin functions as the "receive ds1/e1 line signal" for channel n, within the xrt83l34 device. the user is expected to connect this signal and the corresponding rring_n input signal to a 1:1 transformer. whenever the rtip_n/rring_n input pins are receiving a positive-polarity pulse within the incoming ds1 or e1 line signal, then this input pin will be pulsed to a "higher-voltage" than that of the corresponding rring_n input pin. conversely, whenever the rtip_n/rring_n input pins are receiving a nega - tive-polarity pulse within the incoming ds 1 or e1 line signal, then this input pin will be pulsed to a "lower-voltage" than that of the corresponding rring_n input pin. rring_0 rring_1 rring_2 rring_3 10 22 81 93 i receiver differential ring ne gative input for channel _n: this input pin, along with the correspo nding rtip_n input pin functions as the "receive ds1/e1 line signal" for channel n, within the xrt83l34 device. the user is expected to connect this signal and the corresponding rtip_n input signal to a 1:1 transformer. whenever the rtip_n/rring_n input pins are receiving a positive-polarity pulse within the incoming ds1 or e1 line signal, then this input pin will be pulsed to a "lower-voltage" than that of the corresponding rtip_n input pin. conversely, whenever the rtip_n/rring_n input pins are receiving a nega - tive-polarity pulse within the incoming ds 1 or e1 line signal, then this input pin will be pulsed to a "higher-voltage" than that of the corresponding rtip_n input pin. s ignal n ame p in #t ype d escription
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 7 rxmute rdy_ dtack 73 73 i o receive muting upon los command input/ready or dtack output: the exact function of this input/o utput pin depends upon whether the xrt83l34 device has been configured to operate in the host or hardware mode, as described below. hardware mode operation - receive muting upon los command input pin: this input pin permits the user to enable or disable the "muting upon los" feature within the xrt83l34 device. if the user enables the "muting upon los" feature, then the receive sect ion of each channel (within the xrt83l34 device) will automatically mu te their own rpos_n/rneg_n out - put pins (e.g., force to ground) for th e duration that they are declaring the los defect condition, as described below. low - disables the "muting upon los" feature for all four (4) high - enables the "muting upon los" feature. n otes : 1. internally pulled "low" with 50k ? resistor. 2. in hardware mode, all receive channels share the same rxmute control function. host mode operation - ready or dtack output see ?ready or dtack output/receive muting upon los command input pin:? on page 16. s ignal n ame p in #t ype d escription
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 8 rxres0 rxres1 108 109 i receive external resistor control pins - hardware mode receive external resistor control pin 0 receive external resistor control pin 1 these pins are used to determine the value of the external receive fixed resistor according to the following table: n ote : these pins are internally pulled ?low? with 50k ? resistor. rclke pts1 106 i receive clock edge select/microprocessor type select input pin: the exact function of this input pin depends upon whether the xrt83l34 device has been configured to operate in the host or hardware mode, as described below. hardware mode operation - receive clock edge select input pin - rclke: this input pin permits the user to configure the receive section (of each channel within the xrt83l34 device) to u pdate the data (that is output via the rpos_n/rdata_n and rneg_n/lcv_n output pins) upon either the ris - ing edge or falling edge of the rclk _n output clock signal, as depicted below. low - configures all four channels to update the rpos_n/rdata_n and rneg_n/lcv_n output pins upon rising edge of rclk_n. high - configures all four channel s to update the rpos_n/rdata_n and rneg_n/lcv_n output pins upo n the falling edge of rclk_n. host mode operation - microprocessor type select input pin # 1: this pin is used to select the microprocessor type. see ?microprocessor type select input pins/receive clock edge select/transmit clock edge select input pin:? on page 17. n ote : this pin is internally pulled "low" with a 50k ? resistor. s ignal n ame p in #t ype d escription required fixed external rx resistor no external fixed resistor 240 ? 210 ? 150 ? rxres0 0 1 0 1 rxres1 0 0 1 1
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 9 transmitter sections s ignal n ame p in # t ype d escription tclke pts2 107 i transmit clock edge - hardware mode with this pin set to a "high", transmit input data of all channels are sampled at the rising edge of tclk_n. with this pin tied "low", input data are sampled at the falling edge of tclk_n. microprocessor type select input pin 2 - host mode this pin should be tied to gnd. pts1(pin 106) select s the microprocessor type. see ?microprocessor type select input pins/receive clock edge select/transmit clock edge select input pin:? on page 17. n ote : this pin is internally pulled "low" with a 50k ? resistor. ttip_0 ttip_1 ttip_2 ttip_3 13 19 84 90 o transmitter tip output for channel _n: this output pin, along with the corresponding tring_n output pin, functions as the transmit ds1/e1 output signal drivers for the xrt83l34 device. the user is expected to connect this signal and the corresponding tring_n output signal to a "1:2.45" step-up transformer. whenever the transmit section of (a given channel within the xrt83l34 device) generates and transmits a "positive-polarity" pulse (onto the line), this output pin will be pulsed to a "higher-volt age" than its corresponding tring_n output pins. conversely, whenever the transmit se ction (of a given channel within the xrt83l34 device) generates and transmits a "negative-polarity" pulse (onto the line), then this output pin will be pulsed to a "lower-voltage" than that of the tring_n output pin. n ote : this output pin will be tri-stated wh enever the user sets the "txon" input pin (or bit-field) to "0". tring_0 tring_1 tring_2 tring_3 15 17 86 88 o transmitter ring output for channel _n: this output pin, along with the corre sponding ttip_n output pin, functions as the transmit ds1/e1" output signal drivers for the xrt83l34 device. the user is expected to connect this signal and the corresponding ttip_n output signal to a "1:2.45" step-up transformer. whenever the transmit section (of a given channel, within the xrt83l34 device) generates and transmits a "positive-polarity" pulse (onto the line), this output pin will be pulsed to a "lower-v oltage" than its corresponding ttip_n output pin. conversely, whenever the transmit se ction (of a given channel, within the xrt83l34 device) generates and transmits a "negative-polarity" pulse (onto the line) this output pin will be pulsed to a "higher-voltage" than that of the ttip_n output pin. n ote : this output pin will be tri-stated wh enever the user sets the "txon" input pin (or bit-field) to "0".
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 10 tpos_0/ tdata_0 tpos_1/ tdata_1 tpos_2/ tdata_2 tpos_3/ tdata_3 2 127 104 101 i transmit positive-polarity data in put pin/transmit data input pin: the exact function of this input pin depends upon whether the xrt83l34 device has been configured to operate in the single-rail or dual-mode, as described below. dual-rail mode operation - transmit positive-polarity data output - tpos_n: for dual-rail applications, the system-side terminal equipment should apply the "positive-polarity" port ion of the outbound ds1/e1 data-stream to this input pin. likewise, the system-side terminal equipment should also apply the "negative-polarity" portion of the outbound ds1/e1 data-stream to the tneg_n input pin. the transmit section of channel n will sample this input pin (along with tneg_n) upon the "user-selected" edge of tclk_n. the transmit section of channel n will generate a "positive-pola rity" pulse (via the outbound ds1/e1 line signal) anytime it samples this input pin at a logic "high" level. the transmit section of channel n will no t generate a "positive-polarity" pulse (via the outbound ds1/e1 line signal) an ytime it samples this input pin at a logic "low" level. single-rail mode operation - transmit data output - tdata_n: for single-rail applications, the system-side terminal equipment should apply the entire "outbound" ds1/e1 data-str eam to this input pin. the trans - mit section of channel n will sample this input pin upon the "user-selected" edge of tclk_n. in the single-rail m ode, the internal b8zs/hdb3 encoder will be enabled, and the transmit section of the channel will generate and transmit "positive" and "negative-polari ty" pulses within the outbound ds1/e1 line signal, based upon this "b8zs/hdb3 encoder. n ote : this pin is internally pulled ?low? with a 50k ? resistor for each channels. s ignal n ame p in #t ype d escription
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 11 tneg_0/ codes_0 tneg_1/ codes_1 tneg_2/ codes_2 tneg_3/ codes_3 3 126 105 100 i transmitter negative-polarity data input/line code select input: the exact function of this input pin depends upon the following. ? whether the xrt83l34 device has been configured to operate in the single-rail or dual mode ? whether the xrt83l34 device has been configure to operate in the host or hardware mode, as described below dual-rail mode operation - transmit negative-polarity data input - tneg_n: for dual-rail applications, the system-side terminal equipment should apply the "negative-polarity" portion of the outbound ds1/e1 data-stream to this input pin. likewise, the system-side terminal equipment should also apply the "positive-polarity" portion of t he outbound ds1/e1 data-stream to the tpos_n input pin. the transmit section of channel n will sample this input pin (along with tpos_n) upon the "user-selected" edge of tclk_n. the transmit section of channel n will generate a "negative-polarity" pulse (via the outbound ds1/e1 line signal) anytime it samples this input pin at a logic "high" level. the transmit section of channel n will no t generate a "negative-polarity" pulse (via the outbound ds1/e1 line signal) an ytime it samples this input pin at a logic low" level. single-rail mode operation - line code select input/no function: if the xrt83l34 device has been conf igured to operate in the single-rail mode, then the exact function of this input pin depends upon whether the chip has been configured to operate in the host or hardware mode, as described below. host mode operation - no function: if the xrt83l34 device has been conf igured to operate in both the host mode, and single-rail modes, then this input pin has no function. since this input pin has an internal pull-down resistor, the user can either leave this pin floating, or he/she can tie this pin to gnd. hardware mode operation - line code select input pin - codes_n: if the xrt83l34 device has been config ured to operate in both the hardware and single-rail modes, then this input pin permits the user to configure a given channel to enable or disable the hdb3/b8zs encoder and decoder blocks as described below. if the user enables the hdb3/b8zs encoder and decoder blocks then the channel will support the hdb3 line code (for e1 applications) and the b8zs line code (for t1 applications). if the user disables the hdb3/b8zs encoder and decoder blocks, then the channel will support the ami line code (for either t1 and e1 applications). low - enables the hdb3/b8zs encoder and decoder blocks within channel n. high - disables the hdb3/b8zs enc oder and decoder bl ocks within channel n. n ote : internally pulled ?low? with a 50k ? resistor for channel _n s ignal n ame p in #t ype d escription
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 12 tclk_0 tclk_1 tclk_2 tclk_3 1 128 103 102 i transmit line clock input - channel n: the transmit section of channel n will use this input pin to sample and latch the data that is present on the "tpos _n/tdata_n" and "tneg_n" input pins. this input clock signal also functions as the timing source for the "transmit direction" signal within the channel. for t1 applications, the user is expect ed to apply a 1.544mhz clock signal to this input pin. similarly, for e1 app lications, the user is expected to apply a 2.048mhz clock signal to this input pin. n ote : internally pulled ?low? with a 50k ? resistor for all channels. taos_0 taos_1 taos_2 taos_3 wr _r/ w rd _ ds ale_ as cs 69 70 71 72 69 70 71 72 i transmit all ones command input - channel n: (hardware mode only) the exact function of these input pins depend upon whether the xrt83l34 device has been configured to operate in the host or hardware modes, as described below. hardware mode operation - transmit all ones command input - channel n - taos_n: these input pins permits the user to command a given channel to transmit an "unframed, all ones" pattern (via the outbound ds1/e1 line signal) to the remote terminal equipment. setting this pin to the logic "high" le vel configures the transmit section (of the corresponding channel) to transmit an unframed, all ones pattern via the outbound ds1/e1 line signal. setting this pin to the logic "low" leve l, configures the transmit section (of the corresponding channel) to transmit normal traffic via the outbound ds1/e1 line signal. host mode operation: these pins act as various microprocessor functions. see ?microprocessor interface? on page 13. n ote : these pins are internally pulled ?low? with a 50k ? resistor. txon_0 txon_1 txon_2 txon_3 122 123 124 125 i transmitter turn on for channel _0 hardware mode setting this pin "high" turns on the transmit section of channel _0 and has no control of the channel_0 receiver. when txon_0 = ?0? then ttip_0 and tring_0 driver outputs will be tri-stated. n ote : in hardware mode only, all receiver channels will be turned on upon power-up and there is no provision to power them off. the receive channels can only be independently powered on or off in host mode. in host mode the txon_n bits in the channel control registers turn each channel transmit section on or off. however, control of the on/off function can be transferred to the hardware pins by setting the txonct l bit (bit 6) to ?1? in the register at address hex 0x42. transmitter turn on for channel _1 transmitter turn on for channel _2 transmitter turn on for channel _3 n ote : internally pulled "low" with a 50k ? resistor for all channels. s ignal n ame p in #t ype d escription
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 13 microprocessor interface s ignal n ame p in # t ype d escription hw_ host 68 i host/hardware mode control input pin: this pin permits the user to configure the xrt83l34 device to operate in either the host or the hardware mode. if the user configures the xrt83l34 device to operate in the host mode, then the microprocessor interface block will become active and virtually all configuration settings (within the xrt83l34 device) will be achieved by writ ing values into the on-chip regis - ters (via the microprocessor interface) . if the user configures the xrt83l34 device to operate in the hardware mo de, then the microprocessor interface block will be disabled, and all configuration settings (within the xrt83l34 device) will be achieved by setting various input pins to logic high or low settings. logic low - configures the xrt83l34 device to operate in the host mode. logic high or floating - configures the xrt83l34 device to operate in the hardware mode. n ote : internally pulled ?high? with a 50k ? resistor. wr _r/ w taos_0 69 69 i write strobe/read-write operation identifier/transmit all ones input pin - channel 0: the exact function of this input pin depends upon whether the xrt83l34 device has been configured to operate in the host or the hardware mode, as described below. host mode operation - write strobe/read-write operation identifier: assuming that the xrt83l34 device has been configured to operate in the host mode, then the exact function of the this input pin depends upon which mode the microprocessor interface has been configured to operate in, as described below. intel-asynchronous mode - wr* - write strobe input pin: if the microprocessor interface is confi gured to operate in the intel-asynchro - nous mode, then this input pin functions as the wr* (active-low write strobe) input signal from the microprocessor. once this active-low signal is asserted, then the input buffers (associated with the bi-direction data bus pins, d[7:0]) will be enabled. the micropr ocessor interface will latch the con - tents on the bi-directional data bus (i nto the "target" regi ster or address location, within the xrt83l34) upon the rising edge of this input pin. motorola-asynchron ous mode - r/w* - read/w rite operation identifica - tion input pin: if the microprocessor interface is operating in the "motorola-asynchronous" mode, then this pin is functionally equivalent to the r/w* input pin. in the motorola-asynchronous mode, a read operation occurs if this pin is held at a logic "1", coincident to a falling edge of the rd/ds* (data strobe) input pin. similarly, a write operation occurs if this input is at a logic "0", coincident to a falling edge of the rd/ds* (data strobe) input pin. hardware mode operation - transmit all ?ones? channel_0 - hardware mode see ?transmit all ones command input - channel n: (hardware mode only)? on page 12. n ote : internally pulled ?low? with a 50k ? resistor.
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 14 rd _ ds taos_1 70 70 i read strobe/data strobe/transmit all ones command input - channel 1: the exact function of this input pin depends upon whether the xrt83l34 device has been configure to operate in the host or hardware mode, as described below. host mode operation - read strobe/data strobe input: the exact function of this input pin depends upon which mode the micropro - cessor interface has been configured to operate in, as described below. intel-asynchronous mode - rd* - read strobe input: if the microprocessor interface is oper ating in the intel-asynchronous mode, then this input pin will function as the rd* (active low read strobe) input signal from the microprocesso r. once this active-low signal is asserted, then the xrt83l34 device will place the cont ents of the addressed register on the microprocessor interface bi-directional data bus (d[7:0]). when this signal is negated, then the bi-directional data bus will be tri-stated. motorola-async hronous mode - ds* - data strobe input: if the microprocessor interface is o perating in the moto rola-asynchronous mode, then this input pin will function as the ds* (data strobe) input signal . hardware mode operation - transmit all one command input - channel 1: see ?transmit all ones command input - channel n: (hardware mode only)? on page 12. n ote : internally pulled ?low? with a 50k ? resistor. s ignal n ame p in #t ype d escription
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 15 ale_as taos_2 71 71 i address latch enable/address stro be/transmit all ones input - chan - nel 2: the exact function of this input pin depend upon whether the xrt83l34 device has been configured to operate in the host or hardware mode, as described below. host mode operation - address latch enable/address strobe input pin: the exact function of this input pin depends upon which mode the micropro - cessor interface has been configured to operate in, as described below. intel-asynchronous mode - ale - address latch enable: if the microprocessor interface (of the xrt83l34 device) has been config - ured to operate in the intel-asynchronous mode, then this active-high input pin is used to latch the address (pre sent at the microprocessor interface address bus pins (a[6:0]) into the xrt83l34 microprocessor interface bloc and to indicate the start of a read or write cycle. pulling this input pin "high" enables the input bus drivers for the address bus input pins (a[6:0]). the contents of the address bus will be latched into the xrt83l34 microprocessor interface circuitry, upon the falling edge of this input signal. motorola asynchronous mode - as* - address strobe input: if the microprocessor interface has been configured to operate in the motor - ola-asynchronous mode, then pulling this input pin "low enables the "input" bus drivers for the address bus input pins. during each read or write operation, the user is expected to drive this input pin "low" after (or around the time that) he/she has places the address (of the "target" register) onto the addres s bus pins (a[6:0]). the user is then expected to hold this input pin "low " for the remainder of the read or write cycle. n ote : it is permissible to tie the ale_as* and cs* input pins together.. read and write operations will be performed properly if ale_as is driven "low" coincident to whenever cs* is also driven "low". hardware mode operation - transmit all ?ones? channel_2 - hardware mode see ?transmit all ones command input - channel n: (hardware mode only)? on page 12. n ote : internally pulled ?low? with a 50k ? resistor. cs taos_3 72 72 i chip select input/transmit all ones input - channel 3: the exact function of this input pin depends upon whether the xrt83l34 device has been configured to operate in the host or hardware mode, as described below. host mode operation - chip select input pin: the user must assert this active-low signal in order to select the micropro - cessor interface for read and writ e operations between the microproces - sor and the xrt83l34 on-chip registers. hardware mode operation - transmit all ones input - channel 3: see ?transmit all ones command input - channel n: (hardware mode only)? on page 12. n ote : internally pulled ?low? with a 50k ? resistor. s ignal n ame p in #t ype d escription
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 16 rdy_ dtack rxmute 73 73 o i ready or dtack output/receive mu ting upon los command input pin: the exact function of this input pin depends upon whether the xrt83l34 device has been configured to operate in the host or hardware mode, as described below. host mode operation - ready or dtack output pin: the exact function of this input pin depends upon which mode the micropro - cessor interface has been configured to operate in, as described below. intel-asynchronous mode - rdy* - ready output: if the microprocessor interface has been configured to operate in the intel- asynchronous mode, then th is output pin will function as the "active-low" ready output. during a read or write cycle, the mi croprocessor interface block will tog - gle this output pin to the logic low level, only when it (the microprocessor interface) is ready to complete or terminate the current read or write cycle. once the microprocessor has determined that this input pin has tog - gled to the logic "low" level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or write cycle) t he microprocessor interface block is holding this output pin at a logic "hig h" level, then the microprocessor is expected to extend this read or writ e cycle, until it detects this output pin being toggled to the logic low level. motorola-asynchron ous mode - dtack* - data transfer acknowledge output: if the microprocessor interface has been configured to operate in the motor - ola-asynchronous mode, then this output pin will function as the "active-low" dtack output. during a read or write cycle, the mi croprocessor interface block will tog - gle this output pin to the logic low level, only when it (the microprocessor interface) is ready to complete or terminate the current read or write cycle. once the microprocessor interfac e has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or write cycle) t he microprocessor interface block is holding this output pin at a logic "hig h" level, then the microprocessor is expected to extend this read or writ e cycle, until it detects this output pin being toggled to the logic "low" level. receive muting - hardware mode see ?receive muting upon los command input/ready or dtack output:? on page 7. n ote : internally pulled ?low? with a 50k ? resistor. s ignal n ame p in #t ype d escription
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 17 pts1 pts2 rclke tclke 106 107 106 107 i microprocessor type select input pins/receive clock edge select/ transmit clock edge select input pin: the exact function of these input pins depends upon whether the xrt83l34 device has been configured to operate in the host or hardware mode, as described below. host mode operation - microprocessor type select input bits 2 and 1 - pts[2:1]: these two input pins permit the user to configure the microprocessor inter - face to operate in either of the following modes. ? intel-asynchronous mode ? motorola-asynchronous mode the relationship between the settings of these input pins and the corre - sponding microprocessor interface configuration is presented below. n ote : the pts2 (pin107) should be tied to gnd. the pts1(pin 106) input pin permits the user to selects either the intel-asynchronous or the motorola asynchronous modes. hardware mode operation - receive clock edge select input pin: see ?receive clock edge select/microprocessor type select input pin:? on page 8. hardware mode operation - transmit clock edge select input pin: see ?transmit clock edge - hardware mode? on page 9. n ote : these pins are internally pulled ?low? with a 50k ? resistor. d[7] d[6] d[5] d[4] d[3] d[2]/ d[1]/ d[0]/ loop1_0 loop0_0 loop1_1 loop0_1 loop1_2 loop0_2 loop1_3 loop0_3 42 43 44 45 46 47 48 49 42 43 44 45 46 47 48 49 i/o bi-directional data bus pins/loop-back control input pins - d[7:0]: the exact function of these input/o utput pins depends upon whether the xrt83l34 device has been configured to operate in the host or hardware mode, as described below. host mode operation - bi-directional data bus input/output pins (microprocessor interface block) - d[7:0]: these pins are used to drive and receive data over the bi-directional data bus, whenever the microprocessor performs a read or write operation with the microprocessor interface of the xrt83l34 device. hardware mode operation - loop-back control pin, bits [1:0]_channel_n - hardware mode pins 42 - 49 control which loop-back mode is selected per channel. see ?loop-back control pins - hardware mode:? on page 22. n ote : internally pulled ?low? with a 50k ? resistor. s ignal n ame p in #t ype d escription pts2 pts1 0 0 0 1 p type intel asynchronous mode motorola asynchronous mode
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 18 a[6] a[5] a[4] a[3] a[2] a[1] a[0] jasel1 jasel0 eqc4 eqc3 eqc2 eqc1 eqc0 57 58 59 60 61 62 63 57 58 59 60 61 62 63 i address bus input pins/j itter attenuator select input pins/equalizer control input pins: the exact function of these input pins depends upon whether the xrt83l34 device has been configured to operate in the host or hardware mode, as described below. host mode operation - address bus input pins - a[6:0]: these pins permits the microprocessor to identity on-chip registers (within the xrt83l34 device0 whenever it performs read and write operations with the xrt83l34 device. microprocessor interface address bus[6] microprocessor interface address bus[5] microprocessor interface address bus[4] microprocessor interface address bus[3] microprocessor interface address bus[2] microprocessor interface address bus[1] microprocessor interface address bus[0] jitter attenuator select pins - hardware mode jitter attenuator select pin 1 jitter attenuator select pin 0 see ?jitter attenuator? on page 19. equalizer control pins - hardware mode equalizer control input pin 4 equalizer control input pin 3 equalizer control input pin 2 equalizer control input pin 1 equalizer control input pin 0 pins eqc[4:0] select the receive eq ualizer and transmitter line build out. see ?alarm function//redundancy support? on page 21. n ote : internally pulled ?low? with a 50k ? resistor. int tratio 119 119 i interrupt output - host mode this pin goes ?low? to indicate an alarm condition has occurred within the device. interrupt generation can be globally disabled by setting the gie bit to "0" in the command control register. transmitter transformer ratio select - hardware mode the function of this pin is to select the transmitter transformer ratio. see ?alarm function//redundancy support? on page 21. n ote : this pin is an open drain output and requires an external 10k ? pull- up resistor. s ignal n ame p in #t ype d escription
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 19 jitter attenuator s ignal n ame p in # t ype d escription jasel0 jasel1 a[6] a[5] 58 57 57 58 i jitter attenuator select pins - hardware mode jitter attenuator select pin 0 jitter attenuator select pin 1 jasel[1:0] pins are used to place the jitter attenuator in the transmit path, the receive path or to disable it. microprocessor address bits a[6:5] -host mode see ?address bus input pins/jitte r attenuator select input pins/ equalizer control input pins:? on page 18. n ote : internally pulled ?low? with a 50k ? resistor. disabled transmit receive receive ja path ja bw mhz t1/e1 32/32 32/32 64/64 fifo size t1 3 3 3 e1 10 10 1.5 0 0 0 0 jasel1 0 0 1 1 jasel0 disabled transmit receive receive ja path ja bw hz -------- 32/32 32/32 64/64 fifo size ----- 3 3 3 ----- 10 10 1.5 0 0 1 1 jasel1 0 1 0 1 jasel0 t1 e1
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 20 clock synthesizer s ignal n ame p in # t ype d escription mclke1 32 i e1 master clock input a 2.048mhz clock for with an accuracy of better than 50ppm and a duty cycle of 40% to 60% can be provided at this pin. in systems that have only one master clock source av ailable (e1 or t1), that clock should be connected to both mclke1 and mclkt1 inputs for proper operation. n otes : 1. all channels of the xrt83l34 must be operated at the same clock rate, either t1, e1 or j1. 2. internally pulled ?low? with a 50k ? resistor. clksel0 clksel1 clksel2 37 38 39 i clock select inputs for master clock synthesizer - hardware mode clksel[2:0] are input sign als to a programmable fr equency synthesizer that can be used to generate a master clo ck from an accurate external clock source according to the following table. the mclkrate control signal is gene rated from the state of eqc[4:0] inputs. see table 4 for description of transmit equalizer control bits. host mode: the state of these pins are ignored and the master frequency pll is controlled by the corresponding in terface bits. see register address 1000001. n ote : these pins are internally pulled "low" with a 50k ? resistor. 2048 2048 2048 1544 mclke1 (khz) 8 16 16 56 8 56 64 64 128 256 256 128 2048 2048 1544 1544 mclkt1 (khz) 1544 x x x 1544 x x x x x x x 2048 1544 2048 clkout (khz) 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 0 0 1 1 clksel0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 clksel1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 clksel2 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 1544 2048 x x 2048 1544 0 1 0 1 mclkrate 1 0 1 0 0 1 0 1 1 0 1 0 0 1
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 21 alarm function//redundancy support mclkt1 33 i t1 master clock input this signal is an independent 1.544mhz clock for t1 systems with required accuracy of better than 50ppm and duty cycle of 40% to 60%. mclkt1 input is used in the t1 mode. n otes : 1. all channels of the xrt83l34 must be operated at the same clock rate, either t1, e1 or j1. 2. see pin 32 description for further explanation for the usage of this pin. 3. internally pulled ?low? with a 50k ? resistor. mclkout 36 o synthesized master clock output this signal is the output of the master clock synthesizer pll which is at t1 or e1 rate based upon the mode of operation. s ignal n ame p in # t ype d escription gauge 87 i twisted pair cable wire ga uge select - hardware mode connect this pin "high" to select 26 gauge wire. connect this pin ?low? to select 22 and 24 gauge wire for all channels. n ote : internally pulled ?low? with a 50k ? resistor. dmo_0 dmo_1 dmo_2 dmo_3 64 65 66 67 o driver failure monitor channel _0 this pin transitions "high" if a short circuit condition is detected in the trans - mit driver of channel _0, or no transmit output pulse is detected for more than 128 tclk_0 cycles. driver failure monitor channel _1 driver failure monitor channel _2 driver failure monitor channel _3 ataos 50 i automatic transmit ?all ones? pattern - hardware mode only: a "high" level on this pin enables the automatic transmission of an "all ones" ami pattern from the transmitter of any channel that the rece iver of that chan - nel has detected an los condition. a "low" level on this pin disables this function. n ote : all channels share the same ataos input control function. microprocessor clock input - host mode this pin should be tied to gnd for asynchronous microprocessor modes. n ote : this pin is internally pulled ?low? for asynchronous microprocessor interface when no clock is present. s ignal n ame p in #t ype d escription
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 22 tratio int 119 i o transmitter transformer ratio select - hardware mode in external termination mode (txsel = 0), setting this pin "high" selects a transformer ratio of 1:2 for the transmit ter. a "low" on this pin sets the trans - mitter transformer ratio to 1:2.45. in the internal termination mode the transmitter transformer ratio is permanently set to 1:2 and the state of this pin is ignored. interrupt output - host mode this pin is asserted ?low? to indicate an alarm condition. see ?micropro - cessor interface? on page 13. n ote : this pin is an open drain output and requires an external 10k ? pull- up resistor. reset 121 i hardware reset (active "low") when this pin is tied ?low? for more than 10s, the device is put in the reset state. pulling reset and ict pins ?low? simultaneously will put the chip in factory test mode. this condition should not be permitted during normal operation. n ote : internally pulled ?high? with a 50k ? resistor. sr/ dr 16 i single-rail/dual-rail data format connect this pin "low" to select transmit and receive data format in dual-rail mode . in this mode, hdb3 or b8zs encoder and decoder are not available. connect this pin "high" to select single-rail data format . n ote : internally pulled "low" with a 50k ? resistor. loop1_0 loop0_0 loop1_1 loop0_1 loop1_2 loop0_2 loop1_3 loop0_3 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 42 43 44 45 46 47 48 49 42 43 44 45 46 47 48 49 i/o loop-back control pins - hardware mode: loop-back control pin 1 - channel _0 loop-back control pin 0 - channel _0 loop-back control pin 1 - channel _1 loop-back control pin 0 - channel _1 loop-back control pin 1 - channel _2 loop-back control pin 0 - channel _2 loop-back control pin 1 - channel _3 loop-back control pin 0 - channel _3 microprocessor r/w data bits [7:0] - host mode these pins are microprocessor data bus pins. see ?bi-directional data bus pins/loop-back control input pins - d[7:0]:? on page 17. n ote : these pins are internally pulled ?low? with a 50k ? resistor. s ignal n ame p in #t ype d escription loop1_n loop0_n 0 0 0 1 1 0 1 1 mode normal mode no loop-back channel_n local loop-back channel_n remote loop-back channel_n digital loop-back channel_n
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 23 eqc4 eqc3 eqc2 eqc1 eqc0 a[4] a[3] a[2] a[1] a[0] 59 60 61 62 63 59 60 61 62 63 i equalizer control input 4 - hardware mode this pin together with eqc[3:0] are us ed for controlling the transmit pulse shaping, transmit line build-out (lbo), receive monitoring and also to select t1, e1 or j1 modes of operation. s ee table 4 for description of transmit equalizer control bits. equalizer control input 3 equalizer control input 2 equalizer control input 1 equalizer control input 0 n otes : 1. in hardware mode all transmit channels share the same pulse setting controls function. 2. all channels of an xrt83l34 must operate at the same clock rate, either the t1, e1 or j1 modes. microprocessor address bits [4:0] - host mode see ?address bus input pins/jitte r attenuator select input pins/ equalizer control input pins:? on page 18. n ote : internally pulled ?low? with a 50k ? resistor for all channels. rxtsel 110 i receiver termination select in hardware mode, when this pin is ?low? the receive line termination is determined only by the external resist or. when ?high?, the receive termina - tion is realized by internal resistors or the combination of internal and exter - nal resistors. these conditions are described in the table below. n ote : in hardware mode all channels share the same rxtsel control function. in host mode , the rxtsel_n bits in the channel control registers deter - mines if the receiver termination is external or internal. however the function of rxtsel can be transferred to the hardware pin by setting the tercntl bit (bit 4) to ?1? in the register 66 address hex 0x42. n ote : internally pulled ?low? with a 50k ? resistor. txtsel 111 i transmit termination select - hardware mode when this pin is ?low? the transmit li ne termination is determined only by an external resistor. when ?high?, the transmit termination is realized only by the internal resistor. n otes : 1. this pin is internally pulled "low" with a 50k ? resistor. 2. in hardware mode all channels share the same txtsel control function. s ignal n ame p in #t ype d escription rxtsel rx termination 0 1 external internal txtsel tx termination 0 1 external internal
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 24 tersel0 tersel1 113 112 i termination impedance select pin 0 termination impedance select pin 1 in the hardware mode and in the internal termination mode (txtsel=?1? and rxtsel=?1?), tersel[1:0] control the transmit and receive termination impedance according to the following table. in the internal termination mode , the receiver termination of each receiver is realized completely by internal resi stors or by the combination of internal and one fixed external resistor (s ee description of rxres[1:0] pins). in the internal termination mode the transformer ratio of 1:2 and 1:1 is required for transmitter and receiver re spectively with the transmitter output ac coupled to the transformer. n otes : 1. this pin is internally pulled "low" with a 50k ? resistor. 2. in hardware mode all channels share the same tersel control function. ict 120 i in-circuit testing (active "low"): when this pin is tied ?low?, all output pins are forced to a ?high? impedance state for in-circuit testing. pulling reset and ict pins ?low? simultaneously will put the chip in factory test mode. for normal operation, the user should either leave this input pin "floating" or pull it to a logic "high" level. n ote : internally pulled ?high? with a 50k ? resistor. s ignal n ame p in #t ype d escription 0 1 1 0 1 1 0 0 100 ? 110 ? 75 ? 120 ? termination tersel1 tersel0
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 25 power and ground s ignal n ame p in # t ype d escription tgnd_0 tgnd_1 tgnd_2 tgnd_3 12 20 83 91 **** transmitter analog ground for channel _0 transmitter analog ground for channel _1 transmitter analog ground for channel _2 transmitter analog ground for channel _3 tvdd_0 tvdd_1 tvdd_2 tvdd_3 14 18 85 89 **** transmitter analog po sitive supply (3.3v + 5%) for channel _0 transmitter analog po sitive supply (3.3v + 5%) for channel _1 transmitter analog po sitive supply (3.3v + 5%) for channel _2 transmitter analog po sitive supply (3.3v + 5%) for channel _3 rvdd_0 rvdd_1 rvdd_2 rvdd_3 8 24 79 95 **** receiver analog positive supply (3.3v 5%) for channel _0 receiver analog positive supply (3.3v 5%) for channel _1 receiver analog positive supply (3.3v 5%) for channel _2 receiver analog positive supply (3.3v 5%) for channel _3 rgnd_0 rgnd_1 rgnd_2 rgnd_3 11 21 82 92 **** receiver analog ground for channel _0 receiver analog ground for channel _1 receiver analog ground for channel _2 receiver analog ground for channel _3 vddpll_1 vddpll_2 avdd 30 31 40 **** analog positive supply for master clock synthesizer pll (3.3v 5%) analog positive supply for master clock synthesizer pll (3.3v 5%) analog positive su pply (3.3v 5%) gndpll_1 gndpll_2 agnd 34 35 41 **** analog ground for master clock synthesizer pll analog ground for master clock synthesizer pll analog ground dvdd dvdd dvdd dvdd dvdd dvdd 29 51 52 53 115 116 **** digital positive su pply (3.3v 5%) digital positive su pply (3.3v 5%) digital positive su pply (3.3v 5%) digital positive su pply (3.3v 5%) digital positive su pply (3.3v 5%) digital positive su pply (3.3v 5%) dgnd dgnd dgnd dgnd gnd dgnd dgnd 54 55 56 74 114 117 118 **** digital ground digital ground digital ground digital ground ground digital ground digital ground
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 26 functional description the xrt83l34 is a fully integrated four-channel long-haul and short-haul transceiver intended for t1, j1 or e1 systems. simplified block diagrams of the device are shown in figure 1 , host mode and figure 2 , hardware mode. the xrt83l34 can receive signals that have been a ttenuated from 0 to 36db at 772khz (0 to 6000 feet cable loss) for t1 and from 0 to 43db at 1024khz for e1 systems. in t1 applications, the xrt83l34 can generate five transmi t pulse shapes to meet the short-haul digital cross- connect (dsx-1) template requirement as well as four csu line build-out (lbo) filters of 0db, -7.5db, -15db and -22.5db as required by fcc rules. it also provid es programmable transmit output pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions. the operation and configuration of the xrt83l34 can be controlled through a parallel microprocessor host interface or, by hardware control. master clock generator using a variety of external clock sources, the on-chi p frequency synthesizer generat es the t1 (1.544mhz) or e1 (2.048mhz) master cloc ks necessary for the transmi t pulse shaping and receiv e clock recovery circuit. there are two master clock inputs mclke1 and mclkt1. in systems where both t1 and e1 master clocks are available these clocks can be connected to the respec tive pins. all channels of a given xrt83l34 must be operated at the same clock rate, either t1, e1 or j1 modes. in systems that have only one master cl ock source available (e1 or t1), that clock should be connected to both mclke1 and mclkt1 inputs for proper operation. t1 or e1 master clocks can be generated from 8khz, 16khz, 56khz, 64khz, 128khz and 256khz external cloc ks under the control of clksel[2:0] inputs according to table 1 . n ote : eqc[4:0] determi ne the t1/e1 operating mode. see ta b l e 5 for details. f igure 4. t wo i nput c lock s ource f igure 5. o ne i nput c lock s ource mclke1 mclkt1 mclkout 1.544mhz or 2.048mhz 2.048mhz +/-50ppm 1.544mhz +/-50ppm two input clock sources mclke1 mclkt1 mclkout 1.544mhz or 2.048mhz one input clock source input clock options 8khz 16khz 56khz 64khz 128khz 256khz 1.544mhz 2.048mhz
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 27 in host mode the programming is achieved through the corr esponding interface control bits, the state of the clksel[2:0] control bits an d the state of the mclkra te interface control bit. receiver receiver input at the receiver input, a cable attenuated ami signal can be coupled to the receiver through a capacitor or a 1:1 transformer. the input signal is first applied to a se lective equalizer for signal conditioning. the maximum equalizer gain is up to 36db for t1 and 43db for e1 modes. the equalized signal is subsequently applied to a peak detector which in turn controls t he equalizer settings and the data slicer. the slicer threshold for both e1 and t1 is typically set at 50% of the peak amplitude at the equalizer output. after the slicers, the digital representation of the ami signals are applied to t he clock and data recovery circuit. the recovered data subsequently goes through the jitter attenuator and decoder (if selected) for hdb3 or b8zs decoding before being applied to the rpos_n/rdata_n and rneg_n/lcv_n pins. clock recovery is accomplished by a digital phase-locked loop (dpll) which does not require any ex ternal components and can tolerate high levels of input jitter that meets or exceeds the itu-g.823 and tr-tsy000499 standards. in hardware mode only, all receive channels are turned on upon power-up and are always on. in host mode, each receiver channel can be individually turned on or off with the respective channel rxon_n bit. see ?microprocessor register #0, bit description? on page 63. t able 1: m aster c lock g enerator mclke1 k h z mclkt1 k h z clksel2 clksel1 clksel0 mclkrate m aster c lock k h z 2048 2048 0 0 0 0 2048 2048 2048 0 0 0 1 1544 2048 1544 0 0 0 0 2048 1544 1544 0 0 1 1 1544 1544 1544 0 0 1 0 2048 2048 1544 0 0 1 1 1544 8 x 0 1 0 0 2048 8 x 0 1 0 1 1544 16 x 0 1 1 0 2048 16 x 0 1 1 1 1544 56 x 1 0 0 0 2048 56 x 1 0 0 1 1544 64 x 1 0 1 0 2048 64 x 1 0 1 1 1544 128 x 1 1 0 0 2048 128 x 1 1 0 1 1544 256 x 1 1 1 0 2048 256 x 1 1 1 1 1544
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 28 receive monitor mode in applications where monitor mode is desired, the equa lizer can be configured in a gain mode which handles input signals attenuated resistively up to 29db, along with 0 to 6db cable attenuation for both t1 and e1 applications, refer to table 5 for details. this featur e is available in both hardware and host modes. receiver loss of signal (rlos) for compatibility with itu g.775 require ments, the rlos monitoring func tion is implemen ted using both analog and digital detection schemes. if the analog rlos condition occurs, a digital detector is activated to count for 32 consecutive zeros in e1 (4096 bits in ex tended los mode, exlos = ?1?) or 175 consecutive zeros in t1 before rlos is asserted. rlos is cleared when t he input signal rises +3db (b uilt in hysteresis) above the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more than 16 consecutive zeros for e1. in t1 mode, rlos is cleared when the input signal rises +3db (built in hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more than 100 consecutive zeros in the data stream. when lo ss of signal occurs, rlos register indication and register status will change . if the rlos register enabl e is set high (enabled), t he alarm will trigger an interrupt causing the interrupt pin ( int ) to go low. once the alarm status re gister has been read, it will automatically reset upon read (rur), and the int pin will return high. analog rlos setting the receiver inputs to -15db t1/e1 short haul mode by setting the receiver inputs to -15db t1/e1 short haul mode, the equalizer will detect the in coming amplitude and make adjustments by adding gain up to a maxi mum of +15db normalizing the t1/e1 input signal. n ote : this is the only setting that refers to cabl e loss (frequency), not flat loss (resistive). once the t1/e1 input signal has been normalized to 0db by adding the maximum gain (+15db), the receiver will declare rlos if the signal is atte nuated by an additi onal -9db. the total cable lo ss at rlos declaration is typically -24db (-15db + -9db). a 3db hysteresis was designed so that transients will not trigger the rlos to clear. therefore, the rlos will typically clea r at a total cable atte nuation of -21db. see figure 6 for a simplified diagram. setting the receiver inputs to -29db t1/e1 gain mode by setting the receiver in puts to -29db t1/e1 gain mo de, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +29db normalizing the t1/e1 input signal. n ote : this is the only setting that refers to flat loss (resi stive). all other modes refer to cable loss (frequency). once the t1/e1 input signal has been normalized to 0db by adding the maximum gain (+29db), the receiver will declare rlos if the signal is atte nuated by an additi onal -9db. the total cable lo ss at rlos declaration is f igure 6. s implified d iagram of -15db t1/e1 s hort h aul m ode and rlos c ondition normalized up to +15db max normalized up to +15db max declare los clear los -9db +3db clear los declare los +3db -9db
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 29 typically -38db (-29db + -9db). a 3db hysteresis was designed so that transients will not trigger the rlos to clear. therefore, th e rlos will typically clear at a total flat loss of -35db. see figure 7 for a simplified diagram. setting the receiver inputs to -36db t1/e1 long haul mode by setting the receiver inputs to - 36db t1/e1 long haul mode, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +36db normalizing the t1 input signal. this setting refers to cable loss (frequency), not fl at loss (resistive). once the t1/e1 input signal has been normalized to 0db by adding the maximum gain (+36 db), the receiver will declare rlos if the signal is attenuated by an additional -9db. the total cable loss at rlos declaratio n is typically -45db (-36db + -9db). a 3db hysteresis was designed so that transients will not trigger the rlos to clear. therefore, the rl os will typically clear at a total cable attenuation of -42db. see figure 8 for a simplified diagram. e1 extended rlos e1: setting the receiver inputs to extended rlos by setting the receiver inputs to extended rlos, the equalizer will detect the incoming am plitude and make adjustments by adding gain up to a maximum of +43db normalizing the e1 input signal. this setting refers to cable loss (frequency), not flat loss (resistive). once the e1 input signal has been normalized to 0db by adding the maximum gain (+43db), the receiv er will declare rlos if the signal is attenuated by an additional -9db. the total cable loss at rlos declaration is typically -52db (-43db + -9db). a 3db hysteresis was designed so f igure 7. s implified d iagram of -29db t1/e1 g ain m ode and rlos c ondition f igure 8. s implified d iagram of -36db t1/e1 l ong h aul m ode and rlos c ondition normalized up to +29db max normalized up to +29db max declare los clear los -9db +3db clear los declare los +3db -9db normalized up to +36db max normalized up to +36db max declare los clear los -9db +3db clear los declare los +3db -9db
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 30 that transients will not trigge r the rlos to clear. therefore, the rlos will typically clear at a total cable attenuation of -49db. see figure 9 for a simplified diagram. receive hdb3/b8zs decoder the decoder function is available in both hardware and host modes on a per channel basis by controlling the tneg_n/codes_n pin or the codes_n interface bit. the de coder function is only active in single-rail mode. when selected, receive data in this mode will be decoded according to hdb3 rules for e1 and b8zs for t1 systems. bipolar violations that do not conform to the coding scheme will be reported as line code violation at the rneg_n/lcv_n pin of each channel. the length of the lcv pulse is one rclk cycle for each code violation. in e1mode only, an excessive number of zeros in the receive data stream is also reported as an error at the same output pin. if ami decodi ng is selected in single rail mode, ev ery bipolar violation in the receive data stream will be reported as an error at the rneg_n/lcv_n pin. recovered clock (rclk) sampling edge this feature is available in both hardware and host modes on a global basis. in host mode, the sampling edge of rclk output can be changed through the interf ace control bit rclke. if a ?1? is written in the rclke interface bit, receive data output at rpos_n/rdata_n and rneg_n/lcv_n are updated on the falling edge of rclk for all eight channels. writing a ?0 ? to the rclke register, updates the re ceive data on the rising edge of rclk. in hardware mode the same feature is available under the control of the rclke pin. jitter attenuator f igure 9. s implified d iagram of e xtended rlos mode (e1 o nly ) f igure 10. r eceive c lock and o utput d ata t iming normalized up to +45db max normalized up to +45db max declare los clear los -9db +3db clear los declare los +3db -9db rclk r rclk f rclk rpos or rneg r dy r ho
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 31 to reduce phase and frequency jitter in the recovered cl ock, the jitter attenuator can be placed in the receive signal path. the jitter attenuator uses a data fifo (first in first out) with a progra mmable depth that can vary between 2x32 and 2x64. the jitter attenuator can also be placed in the transmit signal path or disabled altogether depending upon system requirements. the jitter attenuator, other than using the master clock as reference, requires no external components. with the ji tter attenuator selected, the typical throughput delay from input to output is 16 bits for 32 bit fifo size or 32 bits for 64 bit fifo size. when the read and write pointers of the fifo in the jitter attenuator are within tw o bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. when this situation occurs, the jitter a ttenuator will not attenuate input jitter until the read/write pointer's position is outside the two bits window. under normal condition, the jitte r transfer characteristic meets the narrow bandwidth requirement as specified in itu- g.736, itu- i.431 and at&t pub 62411 standards. in t1 mode the jitter attenuator bandwidth is always set to 3hz. in e1 mode, the bandwidth can be reduced through the jabw control signal. when jabw is set ?hi gh? the bandwidth of the jitter attenuator is reduced from 10hz to 1.5hz. under this condition the fifo length is automatically set to 64 bits and the 32 bits fifo length will not be available in this mode. jitter attenuat or controls are available on a per channel basis in the host mode and on a global basis in the hardware mode. gapped clock (ja must be enab led in the transmit path) the xrt83l34 liu is ideal for multip lexer or mapper applications where the network data crosses multiple timing domains. as the higher data rates are de-multiplexed down to t1 or e1 data, stuffing bits are removed which can leave gaps in the incoming data stream. if the ji tter attenuator is enabled in the transmit path, the 32- bit or 64-bit fifo is used to smooth the gapped clock in to a steady t1 or e1 output. the maximum gap width of the 8-channel liu is shown in ta b l e 2 . n ote : if the liu is used in a loop timing system, the jitter attenuator should be enabled in the receive path. t able 2: m aximum g ap w idth for m ultiplexer /m apper a pplications fifo d epth m aximum g ap w idth 32-bit 20 ui 64-bit 50 ui
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 32 arbitrary pulse generator for t1 and e1 the arbitrary pulse generator divides the pulse into eigh t individual segments. each segment is set by a 7-bit binary word by programming the appropriate channel re gister. this allows the system designer to set the overshoot, amplitude, and undershoot for a unique line build out. the msb (bit 7) is a sign-bit. if the sign-bit is set to ?1?, the segment will move in a posit ive direction relative to a flat line (zer o) condition. if this sign-bit is set to ?0?, the segment will move in a negative direction relative to a flat line condition. a pulse with numbered segments is shown in figure 11 . n ote : by default, the arbitrary segments are programmed to 0x00h. the transmitter outputs will result in an all zero pattern to the line. transmitter digital data format both the transmitter and receiver can be configured to operate in dual or single-rail data formats. this feature is available under both hardware and host control modes, on a global basis. the dual or single-rail data format is determined by the state of the sr/ dr pin in hardware mode or sr/ dr interface bit in the host mode. in single-rail mode, transmit clock and nrz data are app lied to tclk_n and tpos_n/tdata_n pins respectively. in single-rail and hardware mode the tneg_n/codes_n input can be used as the codes function. with tneg_n/codes_n tied ?low?, hdb3 or b8zs encoding and decoding are enabled for e1 and t1 modes respectively. with tneg_n/codes_n tied ?high?, the ami coding scheme is selected. in both dual or single- rail modes of operations, the transmitter converts digita l input data to a bipolar format before being transmitted to the line. transmit clock (tclk) sampling edge serial transmit data at tpos_n/tdata_n and tneg_n/codes_n are clocked into the xrt83l34 under the synchronization of tclk_n. with a ?0 ? written to the tclke interface bit, or by pulling the tclke pin ?low?, input data is sampled on t he falling edge of tclk_n. the sampling edge is in verted with a ?1? written to tclke interface bit, or by connec ting the tclke pin ?high?. f igure 11. a rbitrary p ulse s egment a ssignment 1 2 3 4 5 6 7 8 segment register 1 0xn8 2 0xn9 3 0xna 4 0xnb 5 0xnc 6 0xnd 7 0xne 8 0xnf
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 33 transmit hdb3/b8zs encoder the encoder function is available in both hardware and host modes on a per channel basis by controlling the tneg_n/codes_n pin or codes interface bit. the encoder is only available in singl e-rail mode. in e1 mode and with hdb3 encoding selected, any sequence with four or more consecutive zeros in the input serial data from tpos_n/tdata_n, will be remo ved and replaced with 000v or b00v, where ?b? indicates a pulse conforming with the bipolar rule and ?v? representing a pulse violating the rule. an example of hdb3 encoding is shown in ta b l e 3 . in a t1 system, an input data sequence wi th eight or more consecutive zeros will be removed and replaced using the b8zs encoding rule. an example of bipolar with 8 zero substitution (b8zs) encoding scheme is shown in ta b l e 4 . writing a ? 1 ? into the codes_n interface bit or connecting the tneg_n/ codes_n pin to a ?high? le vel selects the ami coding for both e1 or t1 systems. driver failure monitor (dmo) f igure 12. t ransmit c lock and i nput d ata t iming t able 3: e xamples of hdb3 e ncoding n umber of pulse before next 4 zeros n ext 4 bits input 0000 hdb3 (case1) odd 000v hdb3 (case2) even b00v t able 4: e xamples of b8zs e ncoding c ase 1 p receding p ulse n ext 8 b its input + 00000000 b8zs 000vb0vb ami output + 000+ -0- + c ase 2 input - 00000000 b8zs 000vb0vb ami output - 000- +0+ - tclk r tclk f tclk tpos/tdata or tneg t su t ho
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 34 the driver monitor circuit is used to detect transmit driv er failure by monitoring the activities at ttip and tring outputs. driver failure may be caused by a short circui t in the primary transformer or system problems at the transmit input. if the transmitter of a channel has no output for more than 128 clock cycles, the corresponding dmo pin goes ?high? and remains ?high? until a valid transmit pulse is detected. in host mode, the failure of the transmit channel is reported in the corresponding interface bit. if the dmoi e bit is also enabled, any transition on the dmo interface bit will ge nerate an interrupt. th e driver failure monitor is supported in both hardware and host modes on a per channel basis. transmit pulse shaper & line build out (lbo) circuit the transmit pulse shaper circuit uses the high speed clock from the master timing generator to control the shape and width of the transmitted pulse. the internal high-speed timing generator eliminates the need for a tightly controlled transmit cl ock (tclk) duty cycle. with the jitter at tenuator not in the transmit path, the transmit output will generat e no more than 0.025unit interv al (ui) peak-to-peak jitter. in hardware mode, the state of the a[4:0]/eqc[4:0] pins determine the transmit pulse shape for all eight channels. in host mode transmit pulse shape can be controlled on a per channe l basis using the interface bits eqc[4:0]. the chip supports five fixed transmit pulse settings for t1 shor t-haul applications plus a fully programmable waveform generator for arbitrary transmit output pulse shapes. tr ansmit line build-outs for t1 long-haul application are supported from 0db to -22.5db in three 7.5db steps. the choice of the transmit pulse shape and lbo under the control of the interface bits are summarized in ta b l e 5 . for csu lbo transmit pulse design information, refer to ansi t1.403-1993 network-to-cus tomer installation specification, annex-e. n ote : eqc[4:0] determine the t1/e1 operating mode of the xr t83l34. when eqc4 = ?1? and eqc3 = ?1?, the xrt83l34 is in the e1 mode, otherwise it is in the t1/j1 mode. t able 5: r eceive e qualizer c ontrol and t ransmit l ine b uild -o ut s ettings eqc4 eqc3 eq c2 eqc1 eqc0 e1/t1 m ode & r eceive s ensitivity t ransmit lbo c able c oding 0 0 0 0 0 t1 long haul/36db 0db 100 ? / tp b8zs 0 0 0 0 1 t1 long haul/36db -7.5db 100 ? / tp b8zs 0 0 0 1 0 t1 long haul/36db -15db 100 ? / tp b8zs 0 0 0 1 1 t1 long haul/36db -22.5db 100 ? / tp b8zs 0 0 1 0 0 t1 long haul/45db 0db 100 ? / tp b8zs 0 0 1 0 1 t1 long haul/45db -7.5db 100 ? / tp b8zs 0 0 1 1 0 t1 long haul/45db -15db 100 ? / tp b8zs 0 0 1 1 1 t1 long haul/45db -22.5db 100 ? / tp b8zs 0 1 0 0 0 t1 short haul/15db 0-133 ft./ 0.6db 100 ? / tp b8zs 0 1 0 0 1 t1 short haul/15db 133-266 ft./ 1.2db 100 ? / tp b8zs 0 1 0 1 0 t1 short haul/15db 266-399 ft./ 1.8db 100 ? / tp b8zs 0 1 0 1 1 t1 short haul/15db 399-533 ft./ 2.4db 100 ? / tp b8zs 0 1 1 0 0 t1 short haul/15db 533-655 ft./ 3.0db 100 ? / tp b8zs 0 1 1 0 1 t1 short haul/15db arbitrary pulse 100 ? / tp b8zs
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 35 0 1 1 1 0 t1 gain mode/29db 0-133 ft./ 0.6db 100 ? / tp b8zs 0 1 1 1 1 t1 gain mode/29db 133-266 ft./ 1.2db 100 ? / tp b8zs 1 0 0 0 0 t1 gain mode/29db 266-399 ft./ 1.8db 100 ? / tp b8zs 1 0 0 0 1 t1 gain mode/29db 399-533 ft./ 2.4db 100 ? / tp b8zs 1 0 0 1 0 t1 gain mode/29db 533-655 ft./ 3.0db 100 ? / tp b8zs 1 0 0 1 1 t1 gain mode/29db arbitrary pulse 100 ? / tp b8zs 1 0 1 0 0 t1 gain mode/29db 0db 100 ? / tp b8zs 1 0 1 0 1 t1 gain mode/29db -7.5db 100 ? / tp b8zs 1 0 1 1 0 t1 gain mode/29db -15db 100 ? / tp b8zs 1 0 1 1 1 t1 gain mode/29db -22.5db 100 ? / tp b8zs 1 1 0 0 0 e1 long haul/36db itu g.703 75 ? coax hdb3 1 1 0 0 1 e1 long haul/36db itu g.703 120 ? tp hdb3 1 1 0 1 0 e1 long haul/43db itu g.703 75 ? coax hdb3 1 1 0 1 1 e1 long haul/43db itu g.703 120 ? tp hdb3 1 1 1 0 0 e1 short haul itu g.703 75 ? coax hdb3 1 1 1 0 1 e1 short haul itu g.703 120 ? tp hdb3 1 1 1 1 0 e1 gain mode itu g.703 75 ? coax hdb3 1 1 1 1 1 e1 gain mode itu g.703 120 ? tp hdb3 t able 5: r eceive e qualizer c ontrol and t ransmit l ine b uild -o ut s ettings eqc4 eqc3 eq c2 eqc1 eqc0 e1/t1 m ode & r eceive s ensitivity t ransmit lbo c able c oding
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 36 transmit and receive terminations the xrt83l34 is a ve rsatile liu that can be progr ammed to use one bill of ma terials (bom) for worldwide applications for t1, j1 and e1. for specific applications the internal terminations can be disabled to allow the use of existing components and/or designs. receiver (channels 0 - 3) i nternal r eceive t ermination m ode in hardware mode, rxtsel (pin 83) can be tied ?high? to select internal termination mode for all receive channels or tied ?low? to select external termination mode. individual channel control can only be done in host mode. by default the xrt83l34 is set for exte rnal termination mode at power up or at hardware reset. in host mode, bit 7 in the appropriate channel register, ( table 21, ?microprocessor register #1, bit description,? on page 64 ), is set ?high? to select th e internal termination mode for that specific receive channel. if the internal termination mode (rxtsel = ?1?) is selected, the effective impedance for e1, t1 or j1 can be achieved either with an internal resistor or a combi nation of internal and external resistors as shown in ta b l e 7 . n ote : in hardware mode, pins rxres[1:0] control all channels. t able 6: r eceive t ermination c ontrol rxtsel rx termination 0 external 1 internal f igure 13. s implified d iagram for the i nternal r eceive and t ransmit t ermination m ode t1 ttip tring 5 8 1:2 75 ? , 100 ? 110 ? or 120 ? 4 1 0.68 f r int r int ttip tring tx line driver t2 rtip rring 1 4 1:1 8 5 rtip rring rx equalizer r int channel _n tpos tneg tclk rpos rneg rclk 75 ? , 100 ? 110 ? or 120 ?
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 37 figure 14 is a simplified diagram for t1 (100 ? ) in the external rece ive termination mode. figure 15 is a simplified diagram for e1 (75 ? ) in the external receive termination mode. t able 7: r eceive t erminations rxtsel tersel1 tersel0 rxres1 rxres0 r ext r int m ode 0 x x x x r ext t1/e1/j1 1 0 0 0 0 100 ? t1 1 0 1 0 0 110 ? j1 1 1 0 0 0 75 ? e1 1 1 1 0 0 120 ? e1 1 0 0 0 1 240 ? 172 ? t1 1 0 1 0 1 240 ? 204 ? j1 1 1 0 0 1 240 ? 108 ? e1 1 1 1 0 1 240 ? 240 ? e1 1 0 0 1 0 210 ? 192 ? t1 1 0 1 1 0 210 ? 232 ? j1 1 1 0 1 0 210 ? 116 ? e1 1 1 1 1 0 210 ? 280 ? e1 1 0 0 1 1 150 ? 300 ? t1 1 0 1 1 1 150 ? 412 ? j1 1 1 0 1 1 150 ? 150 ? e1 1 1 1 1 1 150 ? 600 ? e1 f igure 14. s implified d iagram for t1 in the e xternal t ermination m ode (rxtsel= 0) 3.1 ? 3.1 ? ttip tring rtip rring xrt83l34 liu 100 ? 100 ? 100 ? 1:2.45 1:1
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 38 transmitter (channels 0 - 3) t ransmit t ermination m ode in hardware mode, txtsel (pin 84) can be tied ?high? to select internal termination mode for all transmit channels or tied ?low? for external terminatio n. individual channel control can be done only in host mode. in host mode, bit 6 in the appropriate register for a given chan nel is set ?high? to select the internal termination mode for that specific transmit channel, see ta b l e 21, ?microprocessor register #1, bit description,? on page 64 . for internal termination, the transformer turns ratio is a lways 1:2. in internal mode, no external resistors are used. an external capacitor of 0.68 f is used for proper operation of the internal termination circuitry, see figure 13 . e xternal t ransmit t ermination m ode by default the xrt83l34 is set for external termination mode at power up or at hardware reset. when external transmit termination mode is selected, the internal termination circuitry is disabled. the value of the external resistors is chosen for a specific applicatio n according to the turns ratio selected by tratio (pin 127) in hardware mode or bit 0 in the appropriate register for a specific channel in host mode, see ta b l e 10 and ta b l e 23, ?microprocessor register #3, bit description,? on page 68 . figure 14 is a simplified block diagram for t1 (100 ? ) in the external termination mode. figure 15 is a simplified blo ck diagram for e1 (75 ? ) in the external termination mode. f igure 15. s implified d iagram for e1 in e xternal t ermination m ode (rxtsel= 0) t able 8: t ransmit t ermination c ontrol txtsel tx termination t x t ransformer r atio 0 external 1:2.45 1 internal 1:2 t able 9: t ermination s elect c ontrol tersel1 tersel0 termination 0 0 100 ? 0 1 110 ? 1 0 75 ? 1 1 120 ? 9.1 ? 9.1 ? ttip tring rtip rring 75 ? xrt83l34 liu 75 ? 75 ? 1:2.45 1:1
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 39 ta b l e 11 summarizes the transmit terminations. redundancy applications telecommunication system de sign requires signal integr ity and reliability. when a t1/e1 primary line card has a failure, it must be swapped with a backup line card while maintaining connectivi ty to a backplane without losing data. system designers can achieve this by implementing common redundancy schemes with the xrt83l34 line interface unit (liu). the xrt83l34 offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. these features allow system designers to implement redun dancy applications that ensur e reliability. the internal impedance mode eliminates the need for external rela ys when using the 1:1 and 1+1 redundancy schemes. t able 10: t ransmit t ermination c ontrol tratio t urns r atio 0 1:2 1 1:2.45 t able 11: t ransmit t erminations tersel1 tersel0 txtsel tratio r int ? n r ext ? c ext 0= external set by control bits n, r ext , and c ext are suggested settings 1= internal t1 100 ? 0 0 0 0 0 ? 2.45 3.1 ? 0 0 0 0 1 0 ? 2 3.1 ? 0 0 0 1 x 12.5 ? 2 0 ? 0.68 f j1 110 ? 0 1 0 0 0 ? 2.45 3.1 ? 0 0 1 0 1 0 ? 2 3.1 ? 0 0 1 1 x 13.75 ? 2 0 ? 0.68 f e1 75 ? 1 0 0 0 0 ? 2.45 6.2 ? 0 1 0 0 1 0 ? 2 9.1 ? 0 1 0 1 x 9.4 ? 2 0 ? 0.68 f e1 120 ? 1 1 0 0 0 ? 2.45 6.2 ? 0 1 1 0 1 0 ? 2 9.1 ? 0 1 1 1 x 15 ? 2 0 ? 0.68 f
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 40 programming considerations in many applications switching the control of the transmitter outputs and the receiver line impedance to hardware control will provide faster transmitter on/off switching. in host mode, there are two bits in register 130 (82h) th at control the transmitter outputs and the rx line impedance select, txoncntl (bit 7) and tercntl (bit 6). setting bit-7 (txoncntl) to a ?1? transfers the cont rol of the transmit on/off function to the txon_n hardware control pins. (pins 90 through 93 and pins 169 through 172). setting bit-6 (tercntl) to a ?1? transfers the contro l of the rx line impedance select (rxtsel) to the rxtsel hardware control pin (pin 83). either mode works well with redundancy applications. the user can determine wh ich mode has the fastest switching time for a unique application. typical redundancy schemes n 1:1 one backup card for every primary card (facility protection) n 1+1 one backup card for every primary card (line protection) n n+1one backup card for n primary cards 1:1 redundancy a 1:1 facility protection redundancy scheme has one backup card for every primary ca rd. when using 1:1 redundancy, the backup card has its transmitters tri-stat ed and its receivers in high impedance. this eliminates the need for external re lays and provides one bill of materials for all inte rface modes of operat ion. the transmit and receive sections of the liu device are described separately. 1+1 redundancy a 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on the backup card are monitoring the receiver inputs. ther efore, the receivers on both cards need to be active. the transmit outputs require no external resistors. t he transmit and receive sections of the liu device are described separately. transmit 1:1 & 1+1 redundancy for 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for internal impedance mode. the transmitters on the backup card should be tri-stated. select the appropriate impedance for the desired mode of operation, t1/e1/j1 . a 0.68uf capacitor is used in series with ttip for blocking dc bias. see figure 16 for a simplified block diagram of the transmit section for 1:1 and 1+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted.
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 41 receive 1:1 & 1+1 redundancy for 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for internal impedance mode. the receivers on the backup card should be pr ogrammed for external impedance mode. since there is no external resistor in th e circuit, the receivers on the backup ca rd will be high impedan ce. this key design feature eliminat es the need for relays a nd provides one bill of materials fo r all interface mo des of operation. select the impedance for the desired mode of operatio n, t1/e1/j1. to swap the pr imary card, se t the backup card to internal impedance mode, then the primary card to external impedance mode. see figure 17 for a simplified block diagram of the receive se ction for a 1:1 and 1+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted. n+1 redundancy f igure 16. s implified b lock d iagram of the t ransmit s ection for 1:1 & 1+1 r edundancy f igure 17. s implified b lock d iagram - r eceive s ection for 1:1 and 1+1 r edundancy t1/e1 line backplane interface primary card backup card xrt83l34 xrt83l34 tx tx line interface card 0.68 f 0.68 f txtsel=1, internal txtsel=1, internal 1:2 or 1:2.45 rxtsel=0, external rxtsel=1, internal backplane interface primary card backup card xrt83l34 xrt83l34 rx line interface card t1/e1 line rx 1:1
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 42 n+1 redundancy has one backup card for n primary card s. due to impedance mismat ch and signal contention, external relays are necessary when using this redundancy scheme. the advantage of relays is that they create complete isolation between the primary cards and the ba ckup card. this allows all transmitters and receivers on the primary cards to be configur ed in internal im pedance mode, providing one bill of materials for all interface modes of operation. the transmit and receiv e sections of the xrt83l34 are described separately. transmit for n+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode providing one bill of materials for t1/e 1/j1. the transmitters on the backup card do not have to be tri-stated. to swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. a 0.68 f capacitor is used in series with ttip for blocking dc bias. see figure 18 for a simplified block diagram of the transmit section for an n+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted. f igure 18. s implified b lock d iagram - t ransmit s ection for n+1 r edundancy backplane interface primary card xrt83l4 tx line interface card 0.68 f t1/e1 line primary card xrt83l34 tx primary card xrt83l34 tx backup card xrt83l34 tx t1/e1 line t1/e1 line txtsel=1, internal txtsel=1, internal txtsel=1, internal txtsel=1, internal 1:2 or 1:2.45 0.68 f 0.68 f 0.68 f 1:2 or 1:2.45 1:2 or 1:2.45
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 43 receive for n+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode. the receivers on the backup card should be programmed for external impedance mode. since there is no external resistor in the circuit, th e receivers on the backup card will be hi gh impedance. select the impedance for the desired mode of operation, t1/e1/j1. to swap the primary card, set the backup card to internal impedance mode, then the primary card to external impedance mode. see figure 19 . for a simplified block diagram of the receive section for a n+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted. f igure 19. s implified b lock d iagram - r eceive s ection for n+1 r edundancy backplane interface primary card xrt83l34 rx line interface card primary card xrt83l34 rx primary card xrt83l34 rx backup card xrt83l34 rx rxtsel=1, internal rxtsel=1, internal rxtsel=1, internal rxtsel=1, external t1/e1 line t1/e1 line t1/e1 line 1:1 1:1 1:1
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 44 pattern transmit and detect function several test and diagnostic patterns can be generated and detected by the chip. in hardware mode each channel can be independently programmed to transmit an all ones pattern by applying a ?high? level to the corresponding taos_n pin. in host mode, the three interface bits txtest[2:0] control the pattern generation and detection independently for each channel according to ta b l e 12 . transmit all ones (taos) this feature is available in both hardware and host modes. with the taos_n pin connected to a ?high? level or when interface bits txtest2=?1?, txtest1=?0? and txtest0=?1? the transmitter ignores input from tpos_n/tdata_n and tneg_n/codes_n pi ns and sends a continuous ami encoded all ?ones? signal to the line, using tclk_n clock as the reference. in addition, when the hardware pin and interface bit ataos is activated, the chip will au tomatically transmit the all ?ones? data from any channel that detects an rlos condition. this feature is not available on a pe r channel basis. tclk_n must not be tied ?low?. network loop code detection and transmission this feature is available in host mode only. when the interface bits txtest2=?1?, txtest1=?1? and txtest0=?0? the chip is enabled to transmit the ?00001? network loop-up code from the selected channel requesting a loop-back condition from the remote te rminal. simultaneously setting the interface bits nlcde1=?0? and nlcde0=?1? enables the network loop-u p code detection in the receiver. if the ?00001? network loop-up code is detected in the receive data fo r longer than 5 seconds, the nlcd bit in the interface register is set indicating that the remote terminal has ac tivated remote loop-back and the chip is receiving its own transmitted data. when the interface bits txtest2=?1?, txtest1=?1? and txtest0=?1? the chip is enabled to transmit the network loop-down code (tldc) ?001? from the selected channel requesting the remote terminal the removal of the loop-back condition. in the host mode each channel is capable of monitoring the contents of the receive data for the presence of loop-up or loop-down code from the remote terminal. in the host mode the two interface bits nlcde[1:0] control the loop-code detection independently for each channel according to ta b l e 13 . setting the interface bits to nlcde1=?0? and nlcde0=?1? activates the detection of the loop-up code in the receive data. if the ?00001? network loop-up code is detected in the receive data for longer than 5 seconds, the nlcd interface bit is set to ?1? and stays in this st ate for as long as the receiver continues to receive the network loop-up code. in this mode if the nlcd interrupt is enabled, the chip will init iate an interrupt on every t able 12: p attern transmission control txtest2 txtest1 txtest0 t est p attern 0 x x none 1 0 0 tdqrss 1 0 1 taos 1 1 0 tluc 1 1 1 tldc t able 13: l oop -c ode d etection c ontrol nlcde1 nlcde0 condition 0 0 disable loop-code detection 0 1 detect loop-up code in receive data 1 0 detect loop-down code in receive data 1 1 automatic loop-code detection and remote loop-back activation
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 45 transition of nlcd. the host has the opti on to ignore the request from the re mote terminal, or to respond to the request and manually activate remote loop-back. the host can subsequently activate the detection of the loop-down code by setting nlcde1=?1 ? and nlcde0=?0?. in this case, re ceiving the ?001? loop-down code for longer than 5 seconds will set the nlcd bit to ?1? and if the nlcd interrupt is enab led, the chip will initiate an interrupt on every transition of nlcd. the host can respond to the request from the remote terminal and remove loop-back condition. in the manual netw ork loop-up (nlcde1=?0? and nlcde0=?1?) and loop- down (nlcde1=?1? and nlcde0=?0?) co de detection modes, the nlcd inte rface bit will be set to ?1? upon receiving the correspond ing code in excess of 5 seconds in the rece ive data. the chip will in itiate an interrupt any time the status of the nlcd bit changes an d the network loop-code interrupt is enabled. in the host mode, setting the interface bits nlcde1=?1? and nlcde0=?1? enables the automatic loop-code detection and remote loop-back activation mode if, tx test[2:0] is not equal to ?110?. as this mode is initiated, the state of the nlcd interface bit is reset to ?0? and the chip is programmed to monitor the receive input data for the loop-up code. if the ?00001? network loop-up code is detected in the receive data for longer than 5 seconds in addition to the nlcd bit in the interface register being set, remote loop-back is automatically activated. the chip stays in remote loop-back even if it stops receiving the ?00001? pattern. after the chip detects the loop-up code, sets the nlcd bit and enters remote loop-back, it automatically starts monitoring the receive data for the loop-down code. in this mode however, the nlcd bit stays set even if the receiver stops receiving the loop-up code, which is an in dication to the host that the remote loop-back is still in effect. remote loop-back is removed if the chip detects the ?001? loop-down code for longer than 5 seconds. detecting the ?001? code also results in resetting the nlcd interf ace bit and initiating an interrupt. the remote loop-back can also be removed by taking the chip out of the automatic detection mode by programming it to operate in a diff erent state. the chip will not respond to remote loop-back request if local analog loop-back is activated locally. when programmed in automatic detection mode the nlcd interface bit stays ?high? for the whole time the remote loop-back is activated and initiates an interrupt any time the status of the nlcd bit changes provided the network loop-code interrupt is enabled. transmit and detect quasi-random signal source (tdqrss) each channel of xrt83l34 includes a qrss pattern gene ration and detection block for diagnostic purposes that can be activated only in the host mode by setting the interface bits txtest2=?1?, txtest1=?0? and txtest0=?0?. for t1 systems, the qrss pattern is a 2 20 -1pseudo-random bit sequence (prbs) with no more than 14 consecutive zeros. for e1 systems, the qrss pattern is 2 15 -1 prbs with an inverted output. with qrss and analog local loop-back enabled simultan eously, and by monitoring the status of the qrpd interface bit, all main functional blocks within the transceiver can be verified. when the receiver achieves qrss sy nchronization with fewer than 4 errors in a 128 bits window, qrpd changes from ?low? to ?high?. after pattern synchronization, any bit erro r will cause qrpd to go ?low? for one clock cycle. if the qrpdie bit is enabled, any tran sition on the qrpd bit will generate an interrupt. with tdqrss activated, a bit error can be inserted in the transmitted qrss pattern by transitioning the insber interface bit from ?0? to ?1?. bipolar violation ca n also be inserted either in the qrss pattern, or input data when operating in the single-rail mode by transitioning t he insbpv interface bit from ?0? to ?1?. the state of insber and insbpv bits are sampled on the rising edge of the tclk_n. to insure the insertion of the bit error or bipolar violation, a ?0? should be writ ten in these bit locations before writing a ?1?.
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 46 loop-back modes the xrt83l34 supports several loop-back modes under both hardware and host control. in hardware mode the two loop[1:0] pins control the loop-back f unctions for each channel independently according to ta b l e 14 . in host mode the loop-back functions are controlled by the three loop[2:0] interface bits. each channel can be programmed independently according to table 15 . local analog loop-back (aloop) with local analog loop-back activated, the transmit data at ttip and tring are looped-back to the analog input of the receiver. external inputs at rtip/rring in this mode are ignored while valid transmit data continues to be sent to the line. local analog loop-ba ck exercises most of the functional blocks of the xrt83l34 including the jitter attenuator which can be sele cted in either the transmit or receive paths. local analog loop-back is shown in figure 20 . in this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path. t able 14: l oop - back control in h ardware mode loop1 loop0 l oop - back m ode 0 0 none 0 1 analog 1 0 remote 1 1 digital t able 15: l oop - back control in h ost mode loop2 loop1 loop0 l oop - back m ode 0 x x none 1 0 0 dual 1 0 1 analog 1 1 0 remote 1 1 1 digital f igure 20. l ocal a nalog l oop - back signal flow rx data & clock recovery decoder tpos tneg tclk rclk rpos rneg tx encoder timing control ja ttip tring rtip rring
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 47 remote loop-back (rloop) with remote loop-back activated, receive data after the jitter attenuator (if selected in the receive path) is looped back to the transmit path using rclk as transmit timing. in this mode transmit clock and data are ignored, while rclk and re ceive data will continue to be available at their respective output pins. remote loop-back with jitter attenuator select ed in the receive path is shown in figure 21 . in the remote loop-back mode if the jitter attenuator is selected in the transmit path, the receive data from the clock and data recovery block is looped back to the trans mit path and is applied to the jitter attenuator using rclk as transmit timing. in this mode the transmit clo ck and data are also ignored, while rclk and received data will continue to be available at their respective output pins. remote loop-back wit h the jitter attenuator selected in the transmit path is shown in figure 22 . f igure 21. r emote l oop - back mode with jitter attenuator selected in receive path f igure 22. r emote l oop - back mode with jitter attenuator selected in t ransmit path tx decoder timing control rx data & clock recovery tpos tneg tclk rclk rpos rneg encoder ttip tring rtip rring ja tx decoder timing control rx clock & data recovery ja tpos tneg tclk rclk rpos rneg encoder ttip trin g rtip rrin g
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 48 digital loop-back (dloop) digital loop-back or local loop-back allows the transmit clock and data to be looped back to the corresponding receiver output pins through the encoder /decoder and jitter attenuator. in this mode, receive data and clock are ignored, bu t the transmit data will be sent to the lin e uninterrupted. this loop back feature allows users to configure the line interface as a pure jitter attenuator. the digital loop-back signal flow is shown in figure 23 . dual loop-back figure 24 depicts the data flow in dual-loopback. in this mo de, selecting the jitter atte nuator in the transmit path will have the same result as placing the jitter attenuator in the receive path. in dual loop-back mode the recovered clock and data from the line are looped back through the transmitter to the ttip and tring without passing through the jitter attenuator. the transmit clock a nd data are looped back through the jitter attenuator to the rclk and rpos/rdata and rneg pins. f igure 23. d igital l oop - back mode with jitter attenuator selected in t ransmit path f igure 24. s ignal flow in d ual loop - back mode tx decoder timing control rx data & clock recovery ja tpos tneg tclk rclk rpos rneg encoder ttip tring rtip rring tx decoder timing control rx data & clock recovery ja tpos tneg tclk rclk rpos rneg encoder ttip tring rtip rring
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 49 the microprocessor interface xrt83l34 is equipped with a microprocessor interface fo r easy device configuration. the parallel port of the xrt83l34 is compatible with both the intel-asynchronous and the motorola-asynchronous address and data buses. the xrt83l34 has an 7-bit address a[6:0] input and 8-bit bi-directional data bus d[7:0]. the pins of the mi croprocessor interface ta b l e 16 presents a list and a brief description of each of the pi ns that make up the microproc essor interface block, within the xrt83l34 device. t able 16: m icroprocessor interface signal description d[7:0] bi-directional data bus pins: these pins are used to drive and receive data over the bi-directional data bus, whenever the micro - processor performs read or write operations wit h the microprocessor inte rface of the xrt83l34 device. a[6:0] address bus input pins: these input pins permit the microprocessor to identi fy on-chip registers (within the xrt83l34 device) whenever it performs read and writ e operations with the xrt83l34 device. pts1 pts2 microprocessor type select: pts2 should be tied to gnd. pts1 selects the microprocessor type. pclk microprocessor clock input : this pin should be tied to gnd for asychronous microprocessor inter - face. n ote : this pin is internally pulled ?low? for asynchronous microprocessor operation when no clock is present. pts2 pts1 0 0 0 1 p type intel asynchronous mode motorola asynchronous mode
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 50 ale_ as address latch enable/address strobe input: the exact function of this input pin depends upo n which mode the microprocessor interface has been configured to operate in, as described below. intel-asynchronous mode - address latch enable - ale: if the microprocessor interface has been configured to operate in the intel-asynchronous mode, then this active-high input pin is used to latch the data (residing on the address bus, a[6:0] into the micro - processor interface circuitry of the xrt83l34 device and to indicate the start of a read or write cycle. pulling this input pin "high" enables the input bus drivers for the address bus input pins. the contents of the address bus will be latched into the micropro cessor interface circuitry, upon the falling edge of this input signal. motorola-asynchrono us mode - address strobe - as*: if the microprocessor interface has been configured to operate in the motorola-asynchronous mode, then pulling this input pin "low enables the "input " bus drivers for the address bus input pins. during each read or write operation, the user is expected to drive this input pin "low" after (or around the time that) he/she has places the add ress (of the "target" register) onto the address bus pins (a[6:0]). the user is then expected to hold this input pin "low" for the remainder of the read or write cycle. n ote : it is permissible to tie the ale_as* and cs* i nput pins together.. re ad and write operations will be performed properly if ale_as is driv en "low" coincident to whenever cs* is also driven "low". cs chip select input: the user must assert this active-low signal in or der to select the micropro cessor interface for read and write operations between the microproc essor and the xrt83l34 on-chip registers. rd_ds read strobe/data strobe input pin: the exact function of this input pin depends upo n which mode the microprocessor interface has been configured to operate in, as described below. intel-asynchronous mode - read strobe input - rd*: if the microprocessor interface is operating in the intel-asynchronous mode, then this input pin will function as the rd* (active-low read strobe) input signal from the microprocessor. once this active-low signal is asserted, then the xrt83l34 device will place the contents of the addressed reg - ister on the microprocessor interface bi-directional data bus (d[7:0]). when this signal is negated, then the data bus will be tri-stated. motorola-asynchronous mode - data strobe input - ds*: if the microprocessor interface is operating in t he motorola-asynchronous mode, then this input pin will function as the ds* (data strobe) input signal. . t able 16: m icroprocessor interface signal description
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 51 wr_r/w write strobe/read-write operation identifier: the exact function of this input pin depends upo n which mode the microprocessor interface has been configured to operate in, as described below. intel-asynchronous mode - write strobe input - wr*: if the microprocessor interface is configured to o perate in the intel-asynchronous mode, then this input pin functions as the wr* (act ive-low, write strobe) input signa l form the microprocessor. once this active-low signal is asserted then the input buffers (associated with the bi-directional data bus pins, d[7:0]) will be enabled. the microprocessor interf ace will latch the contents of the bi-directional data bus (into the "target" register or address loca tion, within the xrt83l34 device) upon the rising edge of this input pin. motorola-asynchronous mode - read/write operation identification input - r/w* if the microprocessor interface is operating in the "motorola-asynchronous" mo de, then this pin is functionally equivalent to the "r/w*" input pin. in the motorola-asynchoronous mode, a read opera - tion occurs if this pin is held at a logic "1", co incident to a falling edge of the rd/ds* (data strobe) input pin. similarly, a write operation occurs if this pin is at a logic "0", coincident to a falling edge of the rd/ds* (data strobe) input pin. rdy_ dtack ready or dtack (data transfer acknowledge) output pin: the exact function of this output pin depends upo n which mode the microprocessor interface has been configured to operate in, as described below. intel-asynchronous mode - ready output - rdy*: if the microprocessor interface has been configured to operate in the intel-asynchronous mode, then this output pin will function as the "active-low" ready output: during a read or write cycle, the microprocessor interface block will toggle this output pin to the logic low level, only when it (the microprocessor in terface) is ready to complete or terminate the cur - rent read or write cycle. if (during a read or write cycle) the microprocessor interface block is holding this output pin at a logic "high" level, then the microprocessor is expec ted to extend this read or write cycle, until it detects this output pin being toggled to the logic "low" level. motorola-asynchronous mode - data tr ansfer acknowledge output - dtack*: if the microprocessor interface has been configured to operate in the motorola-asynchronous mode, then this output pin will function as the "active-low" dtack output. during a read or write cycle, the microprocessor interface will toggle this output pin to the logic "low" level, only when it (the microprocessor interf ace) is ready to complete or terminate the cur - rent read or write cycle. once the microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or write cycle) the microprocessor interface block is holding this output pin at a logic "high" level, then the microprocessor is expec ted to extend this read or write cycle, until it detects this output pin being toggled to the logic "low" level. int interrupt output: this active-low output signal will be asserted (pul led to a logic "low" level) whenever the xrt83l34 device is requesting interrupt service from the mi croprocessor. the activation of this pin can be blocked by setting the gie bit to ?0? in the command control register. t able 16: m icroprocessor interface signal description
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 52 operating the microprocessor interface in the intel-asynchronous mode if the microprocessor interface has been configured to operate in the intel-asynchronous mode, then the following microprocessor in terface pins will assume the role that is described below in table 17. t able 17: t he r oles of the v arious m icroprocessor i nterface p ins , when configured to operate in the i ntel -a synchronous m ode p in n ame d escription t ype p in /b all ale/as address latch enable - ale: if the microprocessor interface has been configured to operate in the intel-asynchronous mode, then this active-high input pin is used to latch the data (residing on the address bus, a[6:0]) into the microprocessor interface circuitry of the xrt83l34 device and to indicate the st art of a read or write cycle. pulling this input pin "high" enables the input bus drivers for the address bus input pins. the contents of the address bus will be latched into the microprocessor interface circuitry upon the falling edge of this input signal. i 71 rd*/ds* read strobe input - rd*: if the microprocessor interface is operating in the intel-asynchro - nous mode, then this input pin wi ll function as the rd* (active-low read strobe) input signal from the microprocessor. once this active-low signal is asserted, then the xrt83l34 device will place the contents of the addressed register on the microprocessor inter - face bi-directional data bus (d[7:0]). when this signal is negated, then the bi-directional data bus will be tri-stated. i 70 rdy_dtack* active low ready output pin - rdy: if the microprocessor interface has been configured to operate in the intel-asynchronous mode, then th is output pin will function as the "active-low" ready output. during a read or write cycle, the microprocessor interface block will toggle this output pin to the logic "low" level, only when it (the microprocessor interface) is ready to complete or ter - minate the current read or wr ite cycle. once the microproces - sor has determined that this input pin has toggled to the logic "low" level, then it is now safe fo r it to move on and execute the next read or write cycle. if (during a read or write cycle) the microprocessor interface block is holding this output pin at a logic "high" level, then the microprocessor is expected to ext end this read or write cycle, until it detects this output pin being toggled to the logic "low" level. o 73 wr*/r/w* write strobe input - wr*: if the microprocessor interface is c onfigured to operate in the intel- asynchronous mode, then this input pin functions as the wr* (active low write strobe) input signal from the microprocessor. once this active-low signal is asserted, then the input buffers (associated with the bi-directio nal data bus, d[7:0]) will be enabled. the microprocessor interface will latch the contents on the bi-directional data bus (into the "target" register or address location, within the xrt83l34 device) upon the rising edge of this input pin. i 69
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 53 configuring the microprocesso r interface to operate in the intel-asynchronous mode the user can configure the microprocessor interface to operate in the intel-asynchronous mode by tying the upts1 (pin 106) to gnd. finally, if the microprocessor interface has been configur ed to operate in the intel-asynchronous mode, then it will perform read and write oper ations as described below. the intel-asynchronous read cycle if the microprocessor interface (of the xrt83l34 device) has been configured to operate in the intel- asynchronous mode, then the microprocessor should do all of the following, anytime it wishes to read out the contents of a register. 1. place the address of the "target" register (within the xrt83l34 device) on the address bus input pins, a[6:0]. 2. while the microprocessor is placing this address value on the address bus, the address decoding circuitry (within the user?s system) should assert the cs* (c hip select) input pin of the xrt83l34 device, by tog - gling it "low". this action enables further communi cation between the microprocessor and the xrt83l34 microprocessor interface block 3. toggle the ale/as (address latch enable) input pin "high". this step enable s the "address bus" input drivers, within the microprocessor interface block of the xrt83l34 device. 4. after allowing the data on the address bus pins to settle (by waiting the appropriate "address data setup time"), the microprocessor should toggle the ale/as input pin "low". this step causes the xrt83l34 device to "latch" the contents of the "address bus" into it s internal circuitry. at th is point, the address of the register (within the xrt83l34 device) has now been selected. 5. next, the microprocessor should indicate that this cu rrent bus cycle is a "read" operation by toggling the "rd*/ds*" (read strobe) input pin "low". this action also enable the bi-directional data bus output driv - ers of the xrt83l34 device. at this point, the "bi-directional" data bu s output drivers will proceed to drive the contents of the "latched" addressed onto the bi-directional data bus, d[7:0]. 6. immediately after the microprocessor toggles the "rea d strobe" (rd*/ds*) signal "low", the xrt83l34 device will continue to drive the rdy*/dtack* output pin "high". the xrt83l34 de vice does this in order to inform the microprocessor that the data (to be read from the data bus) is "not ready" to be "latched" into the microprocessor. in this case, the microproce ssor should continue to hold the "read strobe" (rd*/ ds*) signal "low" until it detects the "rdy*/dtack*" output pin toggling "low". 7. after some settling time, the data on the "bi-directional" data bus will stabilize and can be read by the microprocessor. at this time , the xrt83l34 device will indicate that this data can be re ad by toggling the rdy*/dtack* (ready) signal "low". 8. after the microprocessor detects the rdy*/dtack* signal (from the xrt83l34 device) toggling "low", it can then terminate the read cyc le by toggling the rd*/ds* (read strobe) input pin "high". figure 25 presents a timing diagram that illustrates the behavior of the microprocessor interface signals, during an "intel-
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 54 asynchronous" mode read operation. the intel-asynchronous write cycle if the microprocessor interface (of the xrt83l34 device) has been configured to operate in the intel- asynchronous mode, then the microprocessor should do a ll of the following anytime that it wishes to write a byte of data into a register within the xrt83l34 device. 1. place the address of the "target" register (within the xrt83l34 device) on the address bus input pins, a[6:0]. 2. while the microprocessor is placing the address value on the address bus, the address decoding circuitry (within the user?s system) should assert the cs* (c hip select) input pin of the xrt83l34 device by tog - gling it "low". this action enables further communi cation between the microprocessor and the xrt83l34 microprocessor interface. 3. toggle the ale/as (address latch enable) input pin "high". this step enable s the "address bus" input drivers, within the microprocessor interface block of the xrt83l34 device. 4. after allowing the data on the address bus pins to sett le (by waiting the appropriate "address set-up" time) the microprocessor should toggle the ale/as input pin "low". this step causes the xrt83l34 device to "latch" the contents of the "address bus" into its intern al circuitry. at this point, the address of the register (within the xrt83l34 device) has now been selected. 5. next, the microprocessor should then plac e the byte that it intends to write into the "target" register (within the xrt83l34 device), on the bi-direction data bus pins (d[7:0]). 6. afterwards, the microprocessor should then indicate that this current bus cycle is a "write" operation; by toggling the wr*/r/w (write strobe) input pin "low". this active also enables the "bi-directional" data bus input drivers of the xrt83l34 de vice. at this point, the "bi-directi onal" data bus input drivers will pro - ceed to drive the contents (currently residing on the bi-directional data bus into the register that corre - sponds with the "latched" address. 7. immediately after the microprocessor toggles the "wri te strobe" (wr*/r/w*) signal "low" the xrt83l34 device will continue to drive the "rdy*/dtack*" output pin "high". the xrt83l 34 device does this in order to inform the microprocessor th at the data (to be written into the "target" address location, within the xrt83l34 device) is "not ready" to be latched into the microprocessor interface block circuitry (within f igure 25. i lllustration of an i ntel -a synchronous m ode r ead o peration ale/as rd*/ds* a [6:0] cs* d[7:0] rdy/dtack* not valid valid data address of target register wr*/r/w* microprocessor places ?target? address value on a[6:0] address decoding circuitry asserts cs* rdy* toggles ?low? to indicate that valid data can be read from d[7:0] read operation begins here rdy* toggle ?high? after completion of read o p eration read operation is terminated here microprocessor interface latches contents on a[6:0] upon falling edge of ale
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 55 the xrt83l34 device). in this case, the microprocesso r should continue to hold the "write strobe" (wr*/ r/w*) input pin "low" until it detects the "rdy*/dtack*" output pin toggling "high". 8. after waiting the appropriate amount of time for the data (on the bi -directional data bus) to stabilize and can be safely accepted by the microprocessor interfac e block circuitry (within the xrt83l34 device); the xrt83l34 device will indicate that this data can be latched into the "t arget" address location by toggling the rdy*/dtack* output pin "low". 9. after the microprocessor detects the rdy*/dtack* signal (from the xrt83l34 device) toggling "low", it can then terminate the write cyc le by toggling the wr*/r/w* (write strobe) input pin "high". n ote : once the user toggles the "wr*/r/w* (write strobe) input pin "high", then the microprocessor interface (of the xrt83l34 device) will latch the contents of the bi-directiona l data bus (d[7:0]) into the "target" address location o of the chip. figure _ presents a timing diagram that illustrates the b ehavior of the microprocesso r interface signals during an intel-asynchronous mode write operation. operating the microprocessor interface in the motorola-asynchronous mode if the microprocessor interface has been configured to operate in the motorola-asynchronous mode, then the following microprocessor in terface pins will assume the role t hat is described below in table _. f igure 26. i llustration of an i ntel -a synchronous m ode w rite o peration ale/as rd*/ds* a [6:0] cs* d[7:0] rdy/dtack* data to be written address of target register wr*/r/w* microprocessor places ?target? address value on a[6:0] address decoding circuitry asserts cs* rdy* toggles ?low? to indicate that valid data can be latched into ?target? address location of chi p write operation begins here rdy* toggles ?high? after completion of write o p eration write operation is terminated here microprocessor interface latches contents on a[6:0] upon falling edge of ale
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 56 table _, the roles of various microprocessor interface pins, when configured to operate in the motoro la-asynchronous mode p in n ame p in n umber t ype d escription ale/as 71 i address strobe input - as*: if the microprocessor interface has been configured to operate in the motorola-asynchronous mode, then pulling this input pin "low enables the "input" bus drivers for the address bus input pins. during each read or write operatio n, the user is expected to drive this input pin "low" after (or around t he time that) he/she has places the address (of the "target" register) onto the address bus pins (a[6:0]). the user is then expected to hold this input pin "low" for the remainder of the read or write cycle. n ote : it is permissible to tie the ale_ as* and cs* input pins together.. read and write operations will be performed properly if ale_as is driven "low" coincident to whenever cs* is also driven "low". rd*/ds* 70 i data strobe input - rd*: if the microprocessor interface is operating in the motorola-asynchro - nous mode, then this input pin wi ll function as the ds* (data strobe) input signal. rdy*/ dtack 73 o data transfer acknowledge output - dtack*: if the microprocessor interface has been configured to operate in the motorola-asynchronous mode, then this output pin will function as the "active-low" dtack output. during a read or write cycle, the microprocessor interface block will toggle this output pin to the logic lo w level, only when it (the micropro - cessor interface) is read y to complete or termina te the current read or write cycle. once the microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or write cycle) th e microprocessor interface block is output pin at a logic "high" level, then the microprocessor is expected to extend this read or write cycle, unt il it detects this output pin being toggled to the logic "low" level. wr*/ r/w* 69 i read/write operation identification input - r/w*: if the microprocessor interface is operating in the "motorola-asynchro - nous" mode, then this pin is functionally equivalent to the r/w* input pin. in the motorola mode, a read operation occurs if this pin is held at a logic "1" level, coincident to a fa lling edge of the rd/ds* (data strobe) input pin. similarly, a write operation occurs if this pin is at a logic "0" level, coincident to a falling edge of the rd/ds* (data strobe) input pin.
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 57 configuring the microprocessor interf ace to operate in the motorola- asynchronous mode the user can configure the microprocessor interface to operate in the motorola-asynchronous mode by tying the upts1 (pin 106) to the logic "high" level. finally, if the microprocessor interfac e has been configured to operate in the motorola-asynchronous mode, then it will perform read and writ e operations as described below. the motorola-asynchronous read-cycle: if the microprocessor interface (of the xrt83l34 device) has been configured to operate in the motorola- asynchronous mode, then the microprocessor interface should do all of the following, anytime it wishes to read out the contents of a register within the xrt83l34 device. 1. place the address of the "target" register within the xrt83l34 device, on the address bus input pins, a[6:0]. 2. while the microprocessor is placing the address valu e on the address bus, the address decoding circuitry (within the user?s system) should assert the cs* (chi p select input) pin of the xrt83l34 device, by tog - gling it "low". this action enables further commun ication between the microprocessor and the xrt83l34 microprocessor interface block. 3. assert the ale/as (address strobe) input pin by togg ling it "low". this step enables the address bus input drivers, within the microprocessor interface block of the xrt83l34 device. 4. afterwards, the microprocesso r should indicate that this cycle is a "read" cycle by setting the wr*/r/w* (r/w*) input pin "high". 5. next, the microprocessor should initiate the current bus cycle by toggling the rd*/ds* (data strobe) input pin "low". this step enables the bi-directional data bus output drivers, within the xrt83l34 device. at this point, the bi-directional data bu s output drivers will proceed to drive the contents of the "addressed" register onto the bi-direc tional data bus, d[7:0]. 6. immediately after the microprocessor toggles the "data strobe" (rd*/ds*) signal "low", the xrt83l34 device will continue to drive the rdy*/dtack* output pin "high". the xrt83l34 de vice does this in order to inform the microprocessor that the data (to be read from the data bus) is "not ready" to be latched into the microprocessor. in this case, the microproce ssor should continue to hold the "data strobe" (rd*/ ds*) signal "low" until it detects the "rdy*/dtack*" output pin toggling "low". 7. after some settling time, the data on the "bi-directional" data bus will stabilize and can be read by the microprocessor. the xr t83l34 device will indicate that this data can be read by asserting the rdy*/ dtack* (dtack) output signa l (by toggling it "low"). 8. after the microprocessor detects the rdy*/dtack* signal (from the xrt83l34 device) toggling "low", it can now terminate the ready cycle by toggling the "rd*/ds*" (data strobe) input pin "high". figure _ presents a timing diagram that illustrates the behavio r of the microprocessor interface signals during a "motorola-
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 58 asynchronous" read operation. the motorola-asynchronous write cycle if the microprocessor interface (of the xrt83l34 device) has been configured to operate in the motorola- asynchronous mode, then the microprocessor should do all of the following, anytime it wishes to write a byte of data into a register within the xrt83l34 device. 1. place the address of the "target" register within the xrt83l34 device, on the address bus input pins, a[6:0]. 2. while the microprocessor is placing the address valu e on the address bus, the address decoding circuitry (within the user?s system) should assert the cs* (chi p select) input pin of the xrt83l34 device, by tog - gling it "low". this action enables further communi cation between the microprocessor and the xrt83l34 microprocessor interface. 3. assert the ale/as (address strobe) input pin by toggli ng it "low". this step enables the "address bus" input drivers, within the microprocessor interface block of the xrt83l34 device. 4. afterwards, the microprocesso r interface should indicate that this current bus cycle is a "write" operation by toggling the wr*/r/w* (r/w*) input pin "low". 5. the microprocessor should then place the byte or word th at it intends to write into the "target" register, on the bi-direction data bus, d[7:0]. 6. next, the microprocessor should initiate the bus cycl e by toggling the rd*/ds* (data strobe) input pin "low". when the xrt83l34 device senses that the wr/r/w* (r/w*) input pin is "high" and that the rd*/ds* (data strobe) input pin has toggled "low", it wi ll enable the "input drivers" of the bi-directional data bus, d[7:0]. 7. immediately after the microprocessor toggles the rd*/ds* (data strobe) signal "low", the xrt83l34 device will continue to drive the "rdy*/dtack* outp ut pin "high". the xrt83l34 device does this in order to inform the microprocessor th at the data (to be written into the "target" address location, within the xrt83l34 device) is "not ready" to be latched into the microprocessor interface circuitry (within the xrt83l34 device). in this case, the microprocessor sh ould continue to hold the "data strobe" (rd*/ds*) input pin "low" until it detects the "r dy*/dtack* output pin toggling "high". f igure 27. i lllustration of a m otorola -a synchronous m ode r ead o peration ale/as rd*/ds* a [6:0] cs* d[7:0] rdy/dtack* not valid valid data address of target register wr*/r/w* microprocessor places ?target? address value on a[6:0] address decoding circuitry asserts cs* microprocessor keeps r/w* ?high? to denote read operation read operation begins here dtack* toggles ?low? to indicate that valid data can be read from d [ 7:0 ] read operation is terminated here
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 59 8. after waiting the appropriate time fo r the data (on the bi-directional data bus) to settle and can be safely accepted by the microprocessor, the xrt83l34 device will indicate that th is data can now be latched into the "target" address location by toggling the "rdy*/dtack*" output pin "low. 9. after the microprocessor detects the rdy*/dtack* signal (from the xrt83l34 device) toggling "low", it can then terminate the write cycle by toggling the "rd*/ds*" (data strobe) input pin "high". n ote : once the user toggles the "rd*/ds* (data strobe) input pin "high", then the following two things will happen. 1. the xrt83l34 device will latch the co ntents of the bi-directional data bus into the microprocessor inter - face block. 2. the xrt83l34 device will te rminate the "write" cycle. figure _ presents a timing diagr am that illustrates the behavio r of the microprocessor interface signals, during a "motorola- asynchronous" write operation. f igure 28. i llustration of a m otorola -a synchronous w rite o peration ale/as* a[6:0] cs* d[7:0] rd*/ds* rdy*/dtack* data to be written address of target register wr/r/w* microprocessor places ?target? address value on a[6:0] address decoding circuitry asserts cs* microprocessor toggles ?r/w*? low to denote write o p eration write operation begins here dtack* toggles ?low? to indicate that valid data can be latched into ?target? address location of chip write operation is terminated here
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 60 microprocessor register tables the microprocessor interface consists of 256 addressable locations. each channel uses 16 dedicated 7 bit registers for independent programming and control. there ar e four additional registers for global control of all channels and two registers for device identification and revision numbers. the remaining registers are for factory test and future expansion. the control regist er map and the function of the individual bits are summarized in table 18 and ta b l e 19 respectively. t able 18: m icroprocessor r egister a ddress r egister n umber r egister a ddress f unction hex binary 0 - 15 0x00 - 0x0f 0000000 - 0001111 channel 0 control registers 16 - 31 0x10 -0x1f 0010000 - 00 11111 channel 1 control registers 32 - 47 0x20 - 0x2f 0100000 - 0101111 channel 2 control registers 48 - 63 0x30 - 0x3f 0110000 - 0111111 channel 3 control registers 64 - 67 0x40 - 0x43 1000000 - 1000011 command control registers for all 4 channels 68 - 75 0x44 - 0x4b 1000100 - 1001011 r/w registers reserved for testing purpose. 76-125 0x4c - 0x7d 1001100 - 1111101 reserved 126 0x7e 1111110 device id 127 0x7f 1111111 device revision id t able 19: m icroprocessor r egister b it d escription r eg . # a ddress r eg . t ype b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 channel 0 control registers 0 0000000 hex 0x00 r/w reserved reserved rxon_n eqc4_n eqc3_n eqc2_n eqc1_n eqc0_n 1 0000001 hex 0x01 r/w rxtsel_n txtsel_n tersel1_n tersel0_n jasel1_n jasel0_n jabw_n fifos_n 2 0000010 hex 0x02 r/w invqrss_n txtest2_n txtest1_n txtest0_n txon_n loop2_n loop1_n loop0_n 3 0000011 hex 0x03 r/w nlcde1_n nlcde0_n codes_n rxres1_n rxres0_n insbpv_n insber_n tratio_n 4 0000100 hex 0x04 r/w reserved dmoie_n flsie_n lcvie_n nlcdie_n aisdie_n rlosie_n qrpdie_n 5 0000101 hex 0x05 ro reserved dmo_n fls_n lcv_n nlcd_n aisd_n rlos_n qrpd_n 6 0000110 hex 0x06 rur reserved dmois_n flsis_n lcvis_n nlcdis_n aisdis_n rlosis_n qrpdis_n 7 0000111 hex 0x07 ro reserved reserved clos5_n clos4_n clos3_n clos2_n clos1_n clos0_n 8 0001000 hex 0x08 r/w x b6s1_n b5s1_n b4s1_n b3s1_n b2s1_n b1s1_n b0s1_n
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 61 9 0001001 hex 0x09 r/w x b6s2_n b5s2_n b4s2_n b3s2_n b2s2_n b1s2_n b0s2_n 10 0001010 hex 0x0a r/w x b6s3_n b5s3_n b4s3_n b3s3_n b2s3_n b1s3_n b0s3_n 11 0001011 hex 0x0b r/w x b6s4_n b5s4_n b4s4_n b3s4_n b2s4_n b1s4_n b0s4_n 12 0001100 hex 0x0c r/w x b6s5_n b5s5_n b4s5_n b3s5_n b2s5_n b1s5_n b0s5_n 13 0001101 hex 0x0d r/w x b6s6_n b5s6_n b4s6_n b3s6_n b2s6_n b1s6_n b0s6_n 14 0001110 hex 0x0e r/w x b6s7_n b5s7_n b4s7_n b3s7_n b2s7_n b1s7_n b0s7_n 15 0001111 hex 0x0f r/w x b6s8_n b5s8_n b4s8_n b3s8_n b2s8_n b1s8_n b0s8_n reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 command control global registers for all 8 channels 16-31 001xxxx hex 0x10- 0x1f r/w channel 1control register (see registers 0-15 for description) 32-47 010xxxx hex 0x20- ox2f r/w channel 2 control register (see registers 0-15 for description) 48-63 011xxxx hex 0x30- 0x3f r/w channel 3 control register (see registers 0-15 for description) command control global registers 64 1000000 hex 0x40 r/w sr/ dr ataos rclke tclke datap reserved gie sreset 65 1000001 hex 0x41 r/w e1arben clksel2 clksel1 clksel0 mclkrate rxmute exlos ict 66 1000010 hex 0x42 r/w gauge1 gauge2 txoncntl tercntl sl_1 sl_0 eqg_1 eqg_0 67 1000011 hex 0x43 r/w reserved reserved reserved reserved reserved reserved reserved reserved test registers for channels 0 - 3 68 1000100 hex 0x44 r/w test byte 0 69 1000101 hex 0x45 r/w test byte 1 70 1000110 hex 0x46 r/w test byte 2 71 1000111 hex 0x47 r/w test byte 3 72 1001000 hex 0x48 r/w test byte 4 73 1001001 hex 0x49 r/w test byte 5 t able 19: m icroprocessor r egister b it d escription r eg . # a ddress r eg . t ype b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 62 74 1001010 hex 0x4a r/w test byte 6 75 1001011 hex 0x4b r/w test byte 7 unused registers 76 1001100 hex 0x4c ?. 125 1111101 hex 0x7d id registers 126 1111110 hex 0x7e device id: hex = fb, binary = 1111011 127 1111111 hex 0x7f device revision id t able 19: m icroprocessor r egister b it d escription r eg . # a ddress r eg . t ype b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 63 microprocessor register descriptions t able 20: m icroprocessor r egister #0, b it d escription r egister a ddress 0000000 0010000 0100000 0110000 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6 reserved r/w d5 rxon_n receiver on: writing a ?1? into this bit location turns on the receive section of channel n. writing a ?0? shuts off the receiver section of channel n. n otes : 1. this bit provides independent turn-off or turn-on control of each receiver channel. 2. in hardware mode all receiver channels are always on. r/w 0 d4 eqc4_n equalizer control bit 4: this bit together with eqc[3:0] are used for controlling transmit pulse shaping, transmit line build- out (lbo) and receive monitoring for either t1 or e1 modes of operation. see ta b l e 5 for description of equalizer control bits. r/w 0 d3 eqc3_n equalizer control bit 3: see bit d4 description for function of this bit r/w 0 d2 eqc2_n equalizer control bit 2: see bit d4 description for function of this bit r/w 0 d1 eqc1_n equalizer control bit 1: see bit d4 description for function of this bit r/w 0 d0 eqc0_n equalizer control bit 0: see bit d4 description for function of this bit r/w 0
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 64 t able 21: m icroprocessor r egister #1, b it d escription r egister a ddress 0000001 0010001 0100001 0110001 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 rxtsel_n receiver termination select: in host mode, this bit is used to select between the internal and external line termination modes for the receiver according to the following table; r/w 0 d6 txtsel_n transmit termination select: in host mode, this bit is used to select between the internal and external line termination modes for the transmitter according to the following table; r/w 0 d5 tersel1_n termination impedance select1: in host mode and in internal termination mode, (txtsel = ?1? and rxtsel = ?1?) tersel[1:0] control the transmit and receive termination impedance according to the following table; in the internal termination mode, the receiver termination of each receiver is realized completely by internal resistors or by the combination of internal and one fixed external resistor. in the internal termination mode, the transmitter output should be ac coupled to the transformer. r/w 0 d4 tersel0_n termination impedance select bit 0: see description of bit d5 fo r the function of this bit. r/w 0 rxtsel rx termination 0 1 external internal txtsel tx termination 0 1 external internal tersel1 tersel0 0 0 0 1 1 0 1 1 termination 100 ? 110 ? 75 ? 120 ?
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 65 d3 jasel1_n jitter attenuator select bit 1: the jasel1 and jasel0 bits are used to disable or place the jitter attenuator of each chan - nel independently in the transmit or receive path. r/w 0 d2 jasel0_n jitter attenuator select bit 0: see description of bit d3 for the function of this bit. r/w 0 d1 jabw_n jitter attenuator bandwidth select: in e1 mode, set this bit to ?1? to select a 1.5hz bandwidth for the jitter attenuator. the fifo length will be automatically set to 64 bits. set this bit to ?0? to select 10hz bandwidth for the jitter attenuator in e1 mode. in t1 mode th e jitter attenuator bandwidth is perma - nently set to 3hz, and the state of this bit has no effect on the bandwidth. r/w 0 d0 fifos_n fifo size select: see table of bit d1 above for the function of this bit. r/w 0 t able 21: m icroprocessor r egister #1, b it d escription jasel1 bit d3 jasel0 bit d2 0 0 0 1 1 0 1 1 ja path ja disabled ja in transmit path ja in receive path ja in receive path 0 1 0 1 0 1 0 1 fifos_n bit d0 0 0 1 1 0 0 1 1 jabw bit d1 t1 t1 t1 t1 e1 e1 e1 e1 mode 32 64 32 64 32 64 64 64 fifo size 3 3 3 3 10 10 1.5 1.5 ja b-w hz
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 66 t able 22: m icroprocessor r egister #2, b it d escription r egister a ddress 0000010 0010010 0100010 0110010 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 invqrss_n invert qrss pattern: when tqrss is active, writing a ?1? to this bit inverts the polarity of transmitted qrss pattern. writing a ?0? sends the qrss pattern with no inversion. r/w 0 d6 txtest2_n transmit test pattern bit 2 : this bit together with txtest1 and txtest0 are used to generate and transmit test patterns according to the following table: tdqrss (transmit/detect quasi-random signal): this condition when activated enables quasi-random signal source generation and detection for the selected channel number n. in a t1 system qrss pattern is a 2 20 -1 pseudo- random bit sequence (prbs) with no more than 14 consecu - tive zeros. in a e1 system, qrss is a 2 15 -1 prbs pattern. taos (transmit all ones): activating this condition enables the transmission of an all o nes pattern from the selected channel number n. tluc (transmit network loop-up code): activating this condition enables the network loop-up code of ?00001? to be transmitted to the line for the selected channel number n. when network loop-up code is being transmitted, the xrt83l34 will ignore the automatic loop-code detection and remote loop-back activation (nlcde1 =?1?, nlcde0 =?1?, if activated) in order to avoid activating remote digital loop- back automatically when the remote terminal responds to the loop-back request. tldc (transmit network loop-down code): activating this condition enables the network loop-down code of ?001? to be transmitted to the line for the selected channel number n. r/w 0 d5 txtest1_n transmit test pattern bit 1: see description of bit d6 for the function of this bit. r/w 0 d4 txtest0_n transmit test pattern bit 0: see description of bit d6 for the function of this bit. r/w 0 0 0 0 1 1 0 1 1 1 1 1 1 x x 0 no pattern tdqrss taos tluc test pattern tldc txtest1 txtest0 txtest2
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 67 d3 txon_n transmitter on: writing a ?1? into this bit location turns on the transmit section of channel n. writing a ?0? shuts off the transmit section of channel n. in this mode, ttip_n and tring_n driver outputs will be tri-stated for power reduction or redundancy applications. n ote : this bit provides independent turn-off or turn-on control for each transmitter channel. r/w 0 d2 loop2_n loop-back control bit 2: this bit together with the loop1 and loop0 bits control the loop-back modes of the chip according to the following table: d1 loop1_n loop-back control bit 1: see description of bit d2 for the function of this bit. r/w 0 d0 loop0_n loop-back control bit 0: see description of bit d2 for the function of this bit. r/w 0 t able 22: m icroprocessor r egister #2, b it d escription loop2 0 1 1 1 1 loop1 x 0 0 1 1 loop0 x 0 1 0 1 loop-back mode no loop-back dual loop-back analog loop-back remote loop-back digital loop-back
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 68 t able 23: m icroprocessor r egister #3, b it d escription r egister a ddress 0000011 0010011 0100011 0110011 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 nlcde1_n network loop code de tection enable bit 1: this bit together with nlcde0_n control the loop-code detec - tion of each channel. when nlcde1 =?0? and nlcde0 = ?1? or nlcde1 = ?1? and nlcde0 = ?0?, the chip is ma nually programmed to monitor the receive data for the loop-up or loop-down code respec - tively.when the presence of the ?00001? or ?001? pattern is detected for more than 5 seconds, the status of the nlcd bit is set to ?1? and if the nlcd interr upt is enabled, an interrupt is initiated.the host has the op tion to control the loop-back function manually. setting the nlcde1 = ?1? and nlcde0 = ?1? enables the automatic loop-code detection and remote loop-back acti - vation mode. as this mode is in itiated, the state of the nlcd interface bit is reset to ?0? and the chip is programmed to mon - itor the receive data for the loop-up code. if the ?00001? pat - tern is detected for longer than 5 seconds, the nlcd bit is set ?1?, remote loop-back is activated and the chip is automati - cally programmed to monitor the receive data for the loop- down code. the nlcd bit stays set even after the chip stops receiving the loop-up code. the remote loop-back condition is removed when the chip receives the loop-down code for more than 5 seconds or if the automatic loop-code detection mode is terminated. r/w 0 d6 nlcde0_n network loop code de tection enable bit 0: see description of d7 fo r function of this bit. r/w 0 d5 codes_n encoding and decoding select: writing a ?0? to this bits selects hdb3 or b8zs encoding and decoding for channel number n. writing ?1? selects an ami coding scheme. this bit is only active when single rail mode is selected. r/w 0 nlcde1 nlcde0 0 0 0 1 1 0 1 1 function disable loop-code detection detect loop-up code in receive data detect loop-down code in receive data automatic loop-code detection
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 69 d4 rxres1_n receive external resistor control pin 1: in host mode, this bit along with the rxres0_n bit selects the value of the external receive fixed resistor according to the following table; r/w 0 d3 rxres0_n receive external resistor control pin 0: for function of this bit see description of d4 the rxres1_n bit. r/w 0 d2 insbpv_n insert bipolar violation: when this bit transitions from ?0? to ?1?, a bipolar violation is inserted in the transmitted data stream of the selected channel number n. bipolar violation can be inserted either in the qrss pattern, or input data when operating in single-rail mode. the state of this bit is sampled on the rising edge of the respective tclk_n. n ote : to ensure the insertion of a bipolar violation, a ?0? should be written in this bit location before writing a ?1?. r/w 0 d1 insber_n insert bit error: with tdqrss enabled, when this bit transi - tions from ?0? to ?1?, a bit error will be inserted in the transmit - ted qrss pattern of the select ed channel number n. the state of this bit is sampled on the rising edge of the respective tclk_n. n ote : to ensure the insertion of bit error, a ?0? should be written in this bit location before writing a ?1?. r/w 0 d0 tratio_n transformer ratio select: in the external termination mode, writing a ?1? to this bit selects a transformer ratio of 1:2 for the transmitter. writing a ?0? sets the transmitter transformer ratio to 1:2.45. in the internal termination mode the transmitter transformer ratio is permanently set to 1:2 and the state of this bit has no effect. r/w 0 t able 23: m icroprocessor r egister #3, b it d escription rxres1_n 0 0 required fixed external rx resistor no external fixed resistor 240 ? rxres0_n 0 1 1 1 210 ? 150 ? 0 1
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 70 t able 24: m icroprocessor r egister #4, b it d escription r egister a ddress 0000100 0010100 0100100 0110100 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 dmoie_n dmo interrupt enable: writing a ?1? to this bit enables dmo interrupt generation, writing a ?0? masks it. r/w 0 d5 flsie_n fifo limit status interrupt enable: writing a ?1? to this bit enables interrupt generation when the fifo limit is within to 3 bits, writing a ?0? to masks it. r/w 0 d4 lcvie_n line code violation interrupt enable: writing a ?1? to this bit enables line code violation interrupt generation, writing a ?0? masks it. r/w 0 d3 nlcdie_n network loop-code detection interrupt enable: writing a ?1? to this bit enables network loop-code detection interrupt generation, writing a ?0? masks it. r/w 0 d2 aisdie_n ais interrupt enable: writing a ?1? to this bit enables alarm indication signal detection inte rrupt generation, writing a ?0? masks it. r/w 0 d1 rlosie_n receive loss of signal interrupt enable: writing a ?1? to this bit enables loss of receive signal interrupt generation, writing a ?0? masks it. r/w 0 d0 qrpdie_n qrss pattern detection interrupt enable: writing a ?1? to this bit enables qrss pattern de tection interrupt generation, writing a ?0? masks it. r/w 0
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 71 t able 25: m icroprocessor r egister #5, b it d escription r egister a ddress 0000101 0010101 0100101 0110101 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 dmo_n driver monitor output: this bit is set to a ?1? to indicate transmit driver failure is detected . the value of this bit is based on the current status of dmo for the corresponding channel. if the dmoie bit is enabled, any transition on this bit will gener - ate an interrupt. ro 0 d5 fls_n fifo limit status: this bit is set to a ?1? to indicate that the jit - ter attenuator read/write fifo pointers are within +/- 3 bits. if the flsie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d4 lcv_n line code violation: this bit is set to a ?1? to indicate that the receiver of channel n is currently detecting a line code viola - tion or an excessive number of zeros in the b8zs or hdb3 modes. if the lcvie bit is enabled, any transition on this bit will generate an interrupt. ro 0
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 72 d3 nlcd_n network loop-code detection: this bit operates differently in the manual or the automatic network loop-code detection modes. in the manual loop-code detection mode , (nlcde1 = ?0? and nlcde0 = ?1? or nlcde1 = ?1? and nlcde0 = ?0?) this bit gets set to ?1? as soon as the loop-up (?00001?) or loop- down (?001?) code is detected in the receive data for longer than 5 seconds. the nlcd bit stays in the ?1? state for as long as the chip detects the presence of the loop-code in the receive data and it is reset to ?0? as soon as it stops receiving it. in this mode, if the nlcd in terrupt is enabled, the chip will initiate an interrupt on every transition of the nlcd. when the automatic loop- code detection mode, (nlcde1 = ?1? and nlcde0 =?1?) is init iated, the state of the nlcd interface bit is reset to ?0? and the chip is programmed to mon - itor the receive input data for t he loop-up code. this bit is set to a ?1? to indicate that the ne twork loop code is detected for more than 5 seconds. simultaneously the remote loop-back condition is automatically activated and the chip is pro - grammed to monitor the receive data for the network loop down code. the nlcd bit stays in the ?1? state for as long as the remote loop-back condition is in effect even if the chip stops receiving the loop-up code. remote loop-back is removed if the chip detects the ?001? pattern for longer than 5 seconds in the receive data.detecting the ?001? pattern also results in resetting the nlcd interface bit and initiating an interrupt provided the nlcd interrupt enable bit is active. when programmed in automatic detection mode, the nlcd interface bit stays ?high? fo r the entire time the remote loop-back is active and initiate an interrupt anytime the status of the nlcd bit changes. in this mode, the host can monitor the state of the nlcd bit to determine if the remote loop- back is activated. ro 0 d2 aisd_n alarm indication signal detect: this bit is set to a ?1? to indi - cate all ones signal is detected by the receiver. the value of this bit is based on the current status of alarm indication signal detector of channel n. if the aisdie bit is enabled, any transi - tion on this bit will generate an interrupt. ro 0 d1 rlos_n receive loss of signal: this bit is set to a ?1? to indicate that the receive input signal is lost. the value of this bit is based on the current status of the receive input signal of channel n. if the rlosie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d0 qrpd_n quasi-random pattern detection: this bit is set to a ?1? to indicate the receiver is current ly in synchronization with qrss pattern. the value of this bit is based on the current status of quasi-random pattern detector of channel n. if the qrpdie bit is enabled, any transition on this bit will generate an interrupt. ro 0 t able 25: m icroprocessor r egister #5, b it d escription
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 73 t able 26: m icroprocessor r egister #6, b it d escription r egister a ddress 0000110 0010110 0100110 0110110 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 dmois_n driver monitor output interrupt status: this bit is set to a ?1? every time the dmo status has changed since last read. n ote : this bit is reset upon read. rur 0 d5 flsis_n fifo limit interrupt status: this bit is set to a ?1? every time when fifo limit (read/write pointer with +/- 3 bits apart) sta - tus has changed since last read. n ote : this bit is reset upon read. rur 0 d4 lcvis_n line code violation interrupt status: this bit is set to a ?1? every time when lcv status has changed since last read. n ote : this bit is reset upon read. rur 0 d3 nlcdis_n network loop-code detection interrupt status: this bit is set to a ?1? every time when nlcd status has changed since last read. n ote : this bit is reset upon read. rur 0 d2 aisdis_n ais detection in terrupt status: this bit is set to a ?1? every time when aisd status has changed since last read. n ote : this bit is reset upon read. rur 0 d1 rlosis_n receive loss of signal interrupt status: this bit is set to a ?1? every time rlos status has changed since last read. n ote : this bit is reset upon read. rur 0 d0 qrpdis_n quasi-random pattern detection interrupt status: this bit is set to a ?1? every time when qrpd status has changed since last read. n ote : this bit is reset upon read. rur 0
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 74 t able 27: m icroprocessor r egister #7, b it d escription r egister a ddress 0000111 0010111 0100111 0110111 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 reserved ro 0 d5 clos5_n cable loss bit 5: clos[5:0]_n are the si x bit receive selec - tive equalizer setting which is also a binary word that repre - sents the cable attenuation indication within 1db. clos5_n is the most significant bit (msb) and clos0_n is the least sig - nificant bit (lsb). ro 0 d4 clos4_n cable loss bit 4: see description of d5 for function of this bit. ro 0 d3 clos3_n cable loss bit 3: see description of d5 for function of this bit. ro 0 d2 clos2_n cable loss bit 2: see description of d5 for function of this bit. ro 0 d1 clos1_n cable loss bit 1: see description of d5 for function of this bit. ro 0 d0 clos0_n cable loss bit 0: see description of d5 for function of this bit. ro 0
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 75 t able 28: m icroprocessor r egister #8, b it d escription r egister a ddress 0001000 0011000 0101000 0111000 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s1_n - b0s1_n arbitrary transmit pulse shape, segment 1: the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in ta b l e 5 . the arbitrary pulse is divided into eight time seg - ments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the first time segment. b6s1_n- b0s1_n is in signed magnitude format with b6s1_n as the sign bit and b0s1_n as the least significant bit (lsb). r/w 0 t able 29: m icroprocessor r egister #9, b it d escription r egister a ddress 0001001 0011001 0101001 0111001 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s2_n - b0s2_n arbitrary transmit pulse shape, segment 2 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in ta b l e 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the second time segment. b6s2_n- b0s2_n is in signed magnitude format with b6s2_n as the sign bit and b0s2_n as the least significant bit (lsb). r/w 0
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 76 t able 30: m icroprocessor r egister #10, b it d escription r egister a ddress 0001010 0011010 0101010 0111010 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s3_n - b0s3_n arbitrary transmit pulse shape, segment 3 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in ta b l e 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the third time segment. b6s3_n- b0s3_n is in signed magnitude format with b6s3_n as the sign bit and b0s3_n as the least significant bit (lsb). r/w 0 t able 31: m icroprocessor r egister #11, b it d escription r egister a ddress 0001011 0011011 0101011 0111011 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s4_n - b0s4_n arbitrary transmit pulse shape, segment 4 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in ta b l e 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the fourth time segment. b6s4_n- b0s4_n is in signed magnitude format with b6s4_n as the sign bit and b0s4_n as the least significant bit (lsb). r/w 0
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 77 t able 32: m icroprocessor r egister #12, b it d escription r egister a ddress 0001100 0011100 0101100 0111100 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s5_n - b0s5_n arbitrary transmit pulse shape, segment 5 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in ta b l e 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the fifth time segment. b6s5_n- b0s5_n is in signed magnitude format with b6s5_n as the sign bit and b0s5_n as the least significant bit (lsb). r/w 0 t able 33: m icroprocessor r egister #13, b it d escription r egister a ddress 0001101 0011101 0101101 0111101 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s6_n - b0s6_n arbitrary transmit pulse shape, segment 6 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in ta b l e 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the sixth time segment. b6s6_n- b0s6_n is in signed magnitude format with b6s6_n as the sign bit and b0s6_n as the least significant bit (lsb). r/w 0
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 78 t able 34: m icroprocessor r egister #14, b it d escription r egister a ddress 0001110 0011110 0101110 0111110 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s7_n - b0s7_n arbitrary transmit pulse shape, segment 7 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in ta b l e 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the seventh time segment. b6s7_n-b0s7_n is in signed magnitude format with b6s7_n as the sign bit and b0s7_n as the least significant bit (lsb). r/w 0 t able 35: m icroprocessor r egister #15, b it d escription r egister a ddress 0001111 0011111 0101111 0111111 c hannel _n c hannel _0 c hannel _1 c hannel _2 c hannel _3 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s8_n - b0s8_n arbitrary transmit pulse shape, segment 8 the shape of each channel's transmitted pulse can be made independently user programmable by selecting ?arbitrary pulse? mode in ta b l e 5 . the arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the nth chan - nel's arbitrary pulse during the eighth time segment. b6s8_n- b0s8_n is in signed magnitude format with b6s8_n as the sign bit and b0s8_n as the least significant bit (lsb). r/w 0
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 79 t able 36: m icroprocessor r egister #64, b it d escription r egister a ddress 1000000 n ame f unction r egister t ype r eset v alue b it # d7 sr/ dr single-rail/dual-rail select: writing a ?1? to this bit configures all 8 channels in the xrt83l34 to operate in the single-rail mode. writing a ?0? configures the xrt83l34 to operate in dual-rail mode. r/w 0 d6 ataos automatic transmit all ones upon rlos: writing a ?1? to this bit enables the automatic transmission of all "ones" data to the line for the channel that detects an rlos condition. writing a ?0? disables this feature. r/w 0 d5 rclke receive clock edge: writing a ?1? to this bit selects receive output data of all channels to be updated on the negative edge of rclk. wring a ?0? selects data to be updated on the positive edge of rclk. r/w 0 d4 tclke transmit clock edge: writing a ?0? to this bit selects transmit data at tpos_n/tdata_n an d tneg_n/codes_n of all channels to be sampled on the falling edge of tclk_n. writing a ?1? selects the rising edge of the tclk_n for sam - pling. r/w 0 d3 datap data polarity: writing a ?0? to this bit selects transmit input and receive output data of all channels to be active ?high?. writing a ?1? selects an active ?low? state. r/w 0 d2 reserved 0 d1 gie global interr upt enable: writing a ?1? to this bit globally enables interrupt generation for all channels. writing a ?0? disables interrupt generation. r/w 0 d0 sreset software reset p registers: writing a ?1? to this bit longer than 10s initiates a device reset through the microprocessor interface. all internal circuits are placed in the reset state with this bit set to a ?1? except th e microprocessor register bits. r/w 0
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 80 clock select register the input clock source is used to generate all the ne cessary clock references in ternally to the liu. the microprocessor timing is derived from a pll output whic h is chosen by programming the clock select bits and the master clock rate in register 0x41h. therefore, if the clock selection bits or the mclrate bit are being programmed, the frequen cy of the pll output will be adjusted accordingly. during this adjustment, it is important to "not" write to any other bit location within the same register while sele cting the input/output clock frequency. for best results, whenever the user is changi ng bits d[6:3] (within the clock select register), he/ she should execute a "masked-write" o peration, such that he/she will not cha nge the remaining bits within this register (e.g., d[7] and d[ 2:0] as shown below in figure 29 ). f igure 29. r egister 0 x 81 h s ub r egisters programming examples: example 1: changing bits d[6:3] if bits d[6:3] are the only values wit hin the register that will change in a write process, th e microprocessor only needs to initiate one write operation. example 2: changing bits d[7] and d[2:0] if bits d[7] and d[2:0] are the only values within the register that will change in a write process, the microprocessor only needs to initiate one write operation. example 3: changing bits wit hin d[6:3] and the other bits in this scenario, one must initiate tw o write operations such that bits d[6:3] and the other bits do not change within one write cycle. it is recommended that bits d[6:0] and the ot her bits be treated as two independent sub-registers. one can either change the clock select ion bits and then change bits d[7] and d[2:0] on the second write, or vice-versa. no order or sequence is necessary. d0 d1 d2 d3 d4 d5 d6 d7 clock selection bits exlos, ict e1arben
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 81 t able 37: m icroprocessor r egister #65, b it d escription r egister a ddress 1000001 n ame f unction r egister t ype r eset v alue b it # d7 e1arben e1 arbitrary pulse enable this bit is used to enable the arbitrary pulse generators for shaping the transmit pulse shape when e1 mode is selected. if this bit is set to "1", all 8 channels will be configured for the arbitrary mode. however, each channel is individually con - trolled by programming the channel registers 0xn8 through 0xnf, where n is the number of the channel. "0" = disabled (normal e1 pulse shape itu g.703) "1" = arbitrary pulse enabled r/w 0 d6 clksel2 clock select inputs for master clock synthesizer bit 2: in host mode, clksel[2:0] are inpu t signals to a programma - ble frequency synthesizer that can be used to generate a mas - ter clock from an external accura te clock source according to the following table; in hardware mode, the state of thes e signals are ignored and the master frequency pll is c ontrolled by the corresponding hardware pins. r/w 0 d5 clksel1 clock select inputs for master clock synthesizer bit 1: see description of bit d6 for function of this bit. r/w 0 d4 clksel0 clock select inputs for master clock synthesizer bit 0: see description of bit d6 for function of this bit. r/w 0 d3 mclkrate master clock rate select: the state of this bit programs the master clock synthesizer to generate the t1/j1 or e1 clock. the master clock synthesizer w ill generate the e1 clock when mclkrate = ?0?, and the t1/j1 clock when mclkrate = ?1?. r/w 0 2048 2048 2048 1544 mclke1 khz 8 16 16 56 8 56 64 64 128 256 256 128 2048 2048 1544 1544 mclkt1 khz 1544 x x x 1544 x x x x x x x 2048 1544 2048 clkout/ khz 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 0 0 1 1 clksel0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 clksel1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 clksel2 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 1544 2048 x x 2048 1544 0 1 0 1 mclkrate 1 0 1 0 0 1 0 1 1 0 1 0 0 1
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 82 d2 rxmute receive output mute: writing a ?1? to this bit, mutes receive outputs at rpos/rdata and rneg/lcv pins to a ?0? state for any channel that detects an rlos condition. n ote : rclk is not muted. r/w 0 d1 exlos extended los: writing a ?1? to this bit extends the number of zeros at the receive input of each channel before rlos is declared to 4096 bits. writing a ?0? reverts to the normal mode (175+75 bits for t1 and 32 bits for e1). r/w 0 d0 ict in-circuit-testing: writing a ?1? to this bit configures all the output pins of the chip in hi gh impedance mode for in-circuit- testing. setting the ict bit to ?1? is equivalent to connecting the hardware ict pin 88 to ground. r/w 0 t able 38: m icroprocessor r egister #66, b it d escription r egister a ddress 1000010 n ame f unction r egister t ype r eset v alue b it # d7 gauge1 wire gauge selector bit 1: this bit together with bit d6 are used to select wire gauge size as shown in the table below. r/w 0 d6 gauge0 wire gauge selector bit 0: see bit d7. r/w 0 d5 txoncntl transmit on control: in host mode, setting this bit to ?1 ? transfers the control of the transmit on/off function to the txon_n hardware control pins. n ote : this provides a faster on/off capability for redundancy application. r/w 0 d4 tercntl termination control. in host mode, setting this bit to ?1? transfers the control of the rxtsel to the rxtsel hardware control pin. n ote : this provides a faster on/off capability for redundancy application. r/w 0 t able 37: m icroprocessor r egister #65, b it d escription gauge1 0 1 1 0 gauge0 0 1 0 1 wire size 22 and 24 gauge 26 gauge 24 gauge 22 gauge
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 83 d3 sl_1 slicer level control bit 1: this bit and bit d2 control the slic - ing level for the slicer per the following table. r/w 0 d2 sl_0 slicer level control bit 0: see description bit d3. r/w 0 d1 eqg_1 equalizer gain control bit 1: this bit together with bit d0 control the gain of the equalizer as shown in the table below. r/w 0 d0 eqg_0 equalizer gain control bit 0: see description of bit d1 r/w 0 t able 38: m icroprocessor r egister #66, b it d escription sl_1 sl_0 0 0 0 1 1 0 1 1 slicer mode normal decrease by 5% from normal increase by 5% from normal normal eqg_1 eqg_0 0 0 0 1 1 0 1 1 equalizer gain normal reduce gain by 1 db reduce gain by 3 db normal
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 84 electrical characteristics t able 39: a bsolute m aximum r atings storage temperature...................-65c to + 150c operating temperature.............-40c to + 85c supply voltage..........................-0.5v to + 3.8v v in .................................................-0.5v to + 5.5v t able 40: dc d igital i nput and o utput e lectrical c haracteristics vdd=3.3v5%, t a =25c, unless otherwise specified p arameter s ymbol m in . t yp . m ax . u nits power supply voltage vdd 3.13 3.3 3.46 v input high voltage v ih 2.0 - 5.0 v input low voltage v il -0.5 - 0.8 v output high voltage @ ioh = 2.0ma v oh 2.4 - - v output low voltage @iol = 2ma. v ol - - 0.4 v input leakage current (except input pins with pull-up or pull- down resistor). i l - - 10 a input capacitance c i - 5.0 - pf output load capacitance c l - - 25 pf t able 41: xrt83l34 p ower c onsumption vdd=3.3v5%, t a =25c, unless otherwise specified m ode s upply v oltage i mpedance termination r esistor t ransformer r atio t yp . m ax . u nit t est c onditions r eceiver t ransmitter e1 3.3v 75 ? internal 1:1 1:2 925 1100 mw 100% ?1?s? e1 3.3v 120 ? internal 1:1 1:2 890 1025 mw 100% ?1?s? t1 3.3v 100 ? internal 1:1 1:2 980 1150 mw 100% ?1?s? --- 3.3v --- external --- --- 230 265 mw all transmitters off
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 85 t able 42: e1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a = -40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos de-asserted 10 15 12.5 175 20 255 db db cable attenuation @1024khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 11 db with nominal pulse amplitude of 3.0v for 120 w and 2.37v for 75 w applica - tion. with -18db interference signal added. receiver sensitivity (long haul with cable loss) nominal extended 0 0 36 43 db with nominal pulse amplitude of 3.0v for 120 w and 2.37v for 75 w applica - tion. with -18db interference signal added. input impedance 13 k w input jitter tolerance: 1 hz 10khz-100khz 37 0.2 uipp uipp itu g.823 recovered clock jitter transfer corner frequency peaking amplitude - 36 -0.5 khz db itu g.736 jitter attenuator corner fre - quency (-3db curve) (jabw=0) (jabw=1) - 10 1.5 - hz hz itu g.736 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 14 20 16 - - db db db itu-g.703
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 86 t able 43: t1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos clear 100 15 12.5 175 20 - 250 - - db % ones cable attenuation @772khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 12 - db with nominal pulse amplitude of 3.0v for 100 ? termination receiver sensitivity (long haul with cable loss) 0 - 36 db db with nominal pulse amplitude of 3.0v for 100 w termination input impedance 13 - k w jitter tolerance: 1hz 10khz - 100khz 138 0.4 - - - - uipp at&t pub 62411 recovered clock jitter transfer corner frequency peaking amplitude - - 9.8 - 0.1 khz db tr-tsy-000499 jitter attenuator corner fre - quency (-3db curve) - 6 -hz at&t pub 62411 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 20 25 25 - - - db db db t able 44: e1 t ransmit r eturn l oss r equirement f requency r eturn l oss g.703/ch-ptt ets 300166 51-102khz 8db 6db 102-2048khz 14db 8db 2048-3072khz 10db 8db
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 87 t able 45: e1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 75 w application 120 w application 2.185 2.76 2.37 3.00 2.555 3.24 v v transformer with 1:2 ratio and 9.1 w resistor in series with each end of pri - mary. output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 - itu-g.703 output pulse amplitude ratio 0.95 - 1.05 - itu-g.703 jitter added by the transmitter out - put - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz 8 14 10 - - - - - - db db db etsi 300 166, chptt t able 46: t1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 2.5 3.0 3.5 v use transformer with 1:2.45 ratio and measured at dsx-1 output pulse width 338 350 362 ns ansi t1.102 output pulse width imbalance - - 20 - ansi t1.102 output pulse amplitude imbalance - - + 200 mv ansi t1.102 jitter added by the transmitter out - put - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz - - - 15 15 15 - - - db db db
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 88 f igure 30. itu g.703 p ulse t emplate t able 47: t ransmit p ulse m ask s pecification test load impedance 75 w resistive (coax) 120 w resistive (twisted pair) nominal peak voltage of a mark 2.37v 3.0v peak voltage of a space (no mark) 0 + 0.237v 0 + 0.3v nominal pulse width 244ns 244ns ratio of positive and negative pulses imbalance 0.95 to 1.05 0.95 to 1.05 10% 10% 10% 10% 10% 10% 269 ns (244 + 25) 194 ns (244?50) 244 ns 219 ns (244 ? 25) 488 ns (244 + 244) 0% 50% 20% v = 100% nominal pulse note ? v corresponds to the nominal peak value. 20% 20%
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 89 f igure 31. dsx-1 p ulse t emplate ( normalized amplitude ) t able 48: dsx1 i nterface i solated pulse mask and corner points m inimum curve m aximum curve t ime (ui) n ormalized amplitude t ime (ui) n ormalized amplitude -0.77 -.05v -0.77 .05v -0.23 -.05v -0.39 .05v -0.23 0.5v -0.27 .8v -0.15 0.95v -0.27 1.15v 0.0 0.95v -0.12 1.15v 0.15 0.9v 0.0 1.05v 0.23 0.5v 0.27 1.05v 0.23 -0.45v 0.35 -0.07v 0.46 -0.45v 0.93 0.05v 0.66 -0.2v 1.16 0.05v 0.93 -0.05v 1.16 -0.05v
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 90 t able 49: ac e lectrical c haracteristics vdd=3.3v5%, t a =25c, unless otherwise specified p arameter s ymbol m in . t yp . m ax . u nits e1 mclk clock frequency - 2.048 mhz t1 mclk clock frequency - 1.544 mhz mclk clock duty cycle 40 - 60 % mclk clock tolerance - 50 - ppm tclk duty cycle t cdu 30 50 70 % transmit data setup time t su 50 - - ns transmit data hold time t ho 30 - - ns tclk rise time(10%/90%) tclk r - - 40 ns tclk fall time(90%/10%) tclk f - - 40 ns rclk duty cycle r cdu 45 50 55 % receive data setup time r su 150 - - ns receive data hold time r ho 150 - - ns rclk to data delay rdy - - 40 ns rclk rise time(10% to 90%) with 25pf loading. rclk r - - 40 ns rclk fall time(90% to 10%) with 25pf loading. rclk f 40 ns f igure 32. t ransmit c lock and i nput d ata t iming tclk r tclk f tclk tpos/tdata or tneg t su t ho
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 91 microprocessor interface i/o timing i ntel i nterface t iming - a synchronous the signals used for the intel microprocessor interfac e are: address latch enable (ale), read enable ( rd ), write enable ( wr ), chip select ( cs ), address and data bits. the microprocessor interface uses minimum ex - ternal glue logic and is compatible with the timings of the 8051 or 80188 family of microprocessors. the inter - face timing shown in figure 34 and figure 36 is described in table 50 . f igure 33. r eceive c lock and o utput d ata t iming f igure 34. i ntel a synchronous p rogrammed i/o i nterface t iming rclk r rclk f rclk rpos or rneg r dy r ho addr[6:0] data[7:0] rd_ds wr_r/w rdy_dtack valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 3 t 2 t 4 valid address valid address t 5 t 5 ale_as cs
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 92 t able 50: a synchronous m ode 1 - i ntel 8051 and 80188 i nterface t iming s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to rd assert 65 - ns t 2 rd assert to rdy assert - 50 ns na rd pulse width (t2) 50 - ns t 3 cs falling edge to wr assert 65 - ns t 4 wr assert to rdy assert - 50 ns na wr pulse width (t2) 50 - ns t 5 cs falling edge to as falling edge 0 - ns reset pulse width - both motorola and intel operations (see figure 36 ) t 9 reset pulse width 30
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 93 m otorola a sychronous i nterface t iming the signals used in the motorola microprocessor interface mode are: address strobe (as), data strobe ( ds ), read/write enable (r/ w ), chip select ( cs ), address and data bits. the interface is compatible with the timing of a motorola 68000 microprocessor family. the interface timing is shown in figure 35 and figure 36 . the i/o specifications are shown in ta b l e 51 . f igure 35. m otorola 68k a synchronous p rogrammed i/o i nterface t iming t able 51: a synchronous - m otorola 68k - i nterface t iming s pecification s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to ds assert 65 - ns t 2 ds assert to dtack assert - 50 ns na ds pulse width (t2) 50 - ns t 3 cs falling edge to as falling edge 0 - ns reset pulse width - both motoro la and intel operations (see figure 36 ) t 9 reset pulse width 30 f igure 36. m icroprocessor i nterface t iming - r eset p ulse w idth cs addr[6:0] data[7:0] rd_ds wr_r/w rdy_dtack valid data for readback data available to w rite into the liu read operation write operation t 0 t 0 t 1 t 2 valid address valid address t 3 t 3 t 1 t 2 ale_as reset t 9
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 94 ordering information p art n umber p ackage o perating t emperature r ange xrt83l34iv 128 pin tqfp(14x20x1.4mm) -40 c to +85 c package dimensions - 14x20 mm, 128 pin package e b 1 38 39 64 65 102 103 128 a 2 a a 1 l c e1 e d d1 note: the control dimensions are the millimeter column min max 0.0551 max min 0.8740 0.0079 0.0106 0.0571 0.0059 1.60 1.40 0.0630 0.7835 0.8583 0.0035 0.0067 0.0531 0.0020 0.27 1.45 19.90 21.80 0.09 0.17 1.35 0.15 0.05 0.7913 0.0295 0.5551 0.6378 0.0177 0.0197 bsc 0.5472 0.6220 20.10 22.20 0.20 0.50 bsc 14.10 13.90 16.20 15.80 0.75 millimeters 0.45 0 o 7 o 0 o 7 o symbol d1 d c b a2 a1 a inches l e e1 e
xrt83l34 xr rev. 1.0.1 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 95 revisions r evision d escription a1.0.1 thru a1.0.7 advanced versions p1.1.0 preliminary release version p1.2.0 added ghci_n, sl_1, sl_0, eqg_1 and eqg_0 to control global register 131. separated micropro - cessor description table by register number. moved absolute maximum and dc electrical characteristics before ac electrical characteristics. replaced tbd? s in electrical ables. reformated table of contents. p1.2.1 added gauge1 and gauge0 to control global register 131. corrected control register binary bits. p1.2.2 renamed fifo pin to gauge, edit ed definition and ed ited defintion of jasel[1:0 ] to reflect the fifo size is selected by the jitter attenuator select. p1.2.3 redefined bits d3, d2 and d0 of register 1, in comb ination these bits set the jitter attenuator path and fifo size. p1.2.4 corrected typos in figures 6 and 8. added jitter attenua tor tables in microprocessor register tables. mod - ified microprocessor descrptions, timing di agrams and electrical characteristics. p1.2.5 replaced gchie with reserved in tables 18, 23, 24,25. in the pin list description for int , replace imask bit to a ?1? with gie bit to a ?0?. p1.2.6 new description for bits d6 - d0 in t ables 27 - 34 micr oprocessor registers. p1.2.7 revised microprocessor interface timing diagrams and data. p1.2.8 corrected microprocessor timing information and edited redundancy section. p1.2.9 edited section on rlos for more detailed explanation. p1.3.0 changed definition of txon_n pin. rxon_n bit included in register tables. rx transformer ratio changed from 2:1 to 1:1. description of arbi trary pulse and gap clock support added. p1.3.1 minor edits to block diagram, changed issue date to january, corrected register 67 in table 18, corrected table 37. p1.3.2 swapped the function of pts1 and pts2. replaced processor timing diagrams and timing informa - tion, (figures 29 and 30 -- tables 49 and 50). p1.3.3 updated the power consumption numbers. p1.3.4 added the new e1 arbitrary pulse feature. added descriptions to the global registers. 1.0.0 final release. 1.0.1 added microprocessor section. remo ved sychronous microprocessor modes.
xr xrt83l34 quad t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator rev. 1.0.1 96 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet february 2005. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. notes:

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